Odd cache mappings

I don't expect you faggots to have a clue but I'll try anyway.

Some Core2 processors include non-power-of-two amounts of cache, such as 3MB or 6MB.

How is this cache mapped to addresses?

>>1
Magically.

RAM doesn't need to be a power of two either. Good thing we have MMUs for that sort of stuff, huh?

>>1
One by one. What do you mean? My system has 32-bit addresses. I don't have 4 gigs of RAM. YET MY COMPUTER RUNS

>>4
I don't feel like making the calculations, but he would be right if we didn't have highly complex MMUs (with several different modes for x86) in the hardware that handle that sort of translation for us.

As I expected nobody here knows how caches work.

Let's see, in the 4MB Core 2 case (64-byte cachelines, 8-associative).

You take an address. The lowest 9 bits are the offset inside the cacheline. The next 13 bits decide which of the cacheline groups is going to be used. The rest of the address is stored alongside with the data, to distinguish it from all the data that could go into the same cacheline group.

As you can see, this works nicely for any amount of RAM, but assumes a power-of-2-sized cache.

>>6

Also, I'm retarded: it's the lowest 6 bits the ones who dictate the offset inside the cacheline. Obviously.

>>6
Where in this are you assuming power-of-2-sized sets?

>>8

Fuck, you are right. The "odd" models are, in fact, 12-way set associative.  I never though they would do such a tapestry (and if they did, I'd have expected 6-way associativity).

Well, that's nice.

This reminds me about the computer architecture course I got a C+ in. Excuse me while I return to my toy language which abstracts all this nonsense.

>>10

Any language "abstracts" the cache, even assembly. But it would do you good to know about this stuff, if you ever hope to write anything else than database frontends.

>>3

RAM doesn't need to be a power of two either. Good thing we have MMUs for that sort of stuff, huh?

Congratulations on your total lack of understanding. By the way of MMUs, the cache on anything made in the last decade maps using physical memory addresses, not virtual ones.

>>11
database frontends
I'm more of a Fibonacci guy myself, but your point is taken.

>>6,11
It's stuff like this that makes me grateful for the anonymous board system.

Maybe I should have paid more attention to my computers architecture course when I was a freshman (I'm not >>10, by the way, I got a better grade).

The ENTERPRISE-SCALABLE INTEL® Core™ i7 processor, while providing POWER-OF-2 cache sizes, is empowered by an INDUSTRY-DEFINING level of associativity for its revolutionary L3-cache. At 16, nothing else compares.

>>14
So I said, "Fuck everything, we're doing five caches."

18 Name: Anonymous 2013-09-01 15:16

In 1584, the Italian philosopher and astronomer Giordano Bruno proposed an unbounded universe in On the Infinite Universe and Worlds: "Innumerable suns exist; innumerable earths revolve around these suns in a manner similar to the way the seven planets revolve around our sun. Living beings inhabit these worlds."