Odd cache mappings

I don't expect you faggots to have a clue but I'll try anyway.

Some Core2 processors include non-power-of-two amounts of cache, such as 3MB or 6MB.

How is this cache mapped to addresses?

>>10

Any language "abstracts" the cache, even assembly. But it would do you good to know about this stuff, if you ever hope to write anything else than database frontends.

>>3

RAM doesn't need to be a power of two either. Good thing we have MMUs for that sort of stuff, huh?

Congratulations on your total lack of understanding. By the way of MMUs, the cache on anything made in the last decade maps using physical memory addresses, not virtual ones.