Odd cache mappings

I don't expect you faggots to have a clue but I'll try anyway.

Some Core2 processors include non-power-of-two amounts of cache, such as 3MB or 6MB.

How is this cache mapped to addresses?

As I expected nobody here knows how caches work.

Let's see, in the 4MB Core 2 case (64-byte cachelines, 8-associative).

You take an address. The lowest 9 bits are the offset inside the cacheline. The next 13 bits decide which of the cacheline groups is going to be used. The rest of the address is stored alongside with the data, to distinguish it from all the data that could go into the same cacheline group.

As you can see, this works nicely for any amount of RAM, but assumes a power-of-2-sized cache.