The OOXML standard has over 6000 pages. Microsoft and Intel both design horrible interfaces filled with backwards compatibility kludes but as Ballmer told Otellini: "mine's bigger."
>>1
I'm still waiting for them to document their memory chipset init sequence.
Your move, Cudder.
Name:
Anonymous2013-01-31 0:54
It's not uncommon to have tens of thousands of pages of documentation for really large, really old crap. Especially if you are doing something dangerous like running the security systems that keep the Roswell UFO from returning to the mothership or something.
>>9
Do you have to be fully Jewish to get access, or being circumcised is enough?
By the way, wtf with Wikipedia saying that "nehalem" refers to some indian tribe or something and censoring all mentions of the Hebrew meaning of the word?
>>9 Nehalem
Fucking Shalololololom, KIKE KIKE KIKE. >>10
You have to be fully jewish and participated in at least 5 kidnap-rape-murders of European goy girls ages 5 and unger. With video documentation of each of course.
>>9
And that is why Intel's market penetration outside PCs is terrible. Anybody can write firmware for ARM, but to get into the Intel game you need to either pay an IBV for every unit shipped or be a high tiered customer and get an RSNDA for every employee and their dog.
>>14
If the neckbeards could, they would have already. There's a reason why the only Intel chipsets with support from the coreboot "community" are ancient.
>>17
Some of those steps are just "make sure X" which doesn't count as real code.
And the processor has 3 levels of caches each separately configurable, what did you expect?
Name:
Anonymous2013-02-01 12:09
Marry me, Cudder!
Name:
Anonymous2013-02-01 16:01
>>15
What reason would that be? My guess is that the coreboot community have chosen to invest their time on other chipsets. I bet there're plenty of EE gradutates who would accept thousands for the job of reversing newer chipsets and porting coreboot to them..
>>13
Nobody would use the x86 instruction set if it wasn't for PCs either. Intel spends time and money on 16-bit modes that address less than a thousandth of the RAM and ``conventional'' memory holes to mimic a 70's CPU in case someone wants to run DOS at 3 GHz, not to mention the instructions and segmentation mechanisms that nobody ever uses.
>>21
Backwards compatibility is very important, and is one of the main reasons to choose x86. The older addressing modes are well known and no more "time and money" needs to be spent on them anyway, since they essentially copy+paste much of the design from the previous generation for their base.
They're probably still mad at AMD for making a horrible mess of what they wanted the 64-bit mode to look like. There are so many empty spaces in the opcode map that could've been used for 64-bit extension prefices, and segment descriptors have additional empty bits that could've easily accommodated 16, 32, and 64-bit coexistence, letting you use 64-bit operations in real mode just like it was possible with 32-bit, but they decided to overwrite an entire row of register inc/decs and introduce entirely incompatible operation modes.
But pissing off Intel by trying to make them start over with the architecture was probably a bad idea. And they had to put back some of the stuff they stupidly "left out" but was always there, since the circuitry is still present on die!
Name:
Anonymous2013-02-02 23:53
>>25
Intel didn't want 64-bit x86 to look like anything. You know you're in trouble with an ISA when even the company that created it doesn't want to deal with it anymore.
Name:
Anonymous2013-02-03 0:00
הקונבולוציה שהיא x86 היא למעשה שום פיתול, אבל עליונות. בחייך, אתה יודע שאתה כמו מצב של 16-bit מפולח פונה. אתם כמהים לאותם ימים.
Name:
Anonymous2013-02-03 0:13
>>25 Backwards compatibility is very important, and is one of the main reasons to choose x86.
Yeah. That is the reason for their filthy Jewish monopoly. Fuck, I hate Jews so much: first they did Christfaggotry, nuclear bomb, now x86. Every single evil thing comes Jews.
Name:
Anonymous2013-02-03 0:45
>>26
They still have the ugly one-operand divide instruction that can't take immediates, the parity bit which is hardly ever used because it's untestable by portable languages, the stack-based x87 that makes things harder for compilers, a Z80-compatible flags register, no absolute CALL, booting in real mode (which has less address space than the cache of some new CPUs), and all of those other warts in the instruction set.
>>29
If you're using a lot of integer division, you're doing it wrong. You can compute parity & popcount using the traditional BSR and BSF instructions (most C/C++ compilers provide intrinsics for these) or the new POPCNT and LZCNT instructions on SSE 4.2 enabled CPUs. x87 is deprecated. Everyone uses SSE/AVX on x86/x86-64 these days. The MSVC, ICC, GCC, Clang etc. don't even touch the x87 opcodes when generating code for x86-64, unless you explicitly force it too. GCC only generates x87 for long double, other compilers have sizeof(long double) == sizeof(double). The ISA is largely divorced from the actual microcode execution engine which is very RISC like. The other stuff is just pedantic crap that only faggots like you care about.
>>26
I'm pretty sure Intel were designing 64-bit x86, AMD just got to the market first.
They still have the ugly one-operand divide instruction that can't take immediates
As if MIPS' completely separate result registers and arcane timing requirements are any better? And ARM didn't even have a divide instruction until very recently...
parity bit which is hardly ever used because it's untestable by portable languages
So what? If the language doesn't let you use the full functionality of the CPU then it's the language's fault.
stack-based x87 that makes things harder for compilers
Again, it's the compiler writers that need to get smarter. And if anything, stack-based ISAs are far easier to generate code for than register-based.
a Z80-compatible flags register
So what?
no absolute CALL
Because relative calls have advantages over absolutes and can't be easily simulated by absolutes (relocation etc.), but the opposite is not true.
booting in real mode
So what? You get backwards compatibility for free, and can switch into protected mode if needed; it's only 4 instructions or so, and you get to decide what the GDT should be. Intel did try making a CPU that booted in protected mode, the 80376, and it failed miserably: you still needed to setup the protected mode stuff, and lost the ability to run existing code, so there was absolutely no advantage.
which has less address space than the cache of some new CPUs
Ever tried DOS benchmarks on a late-model i7? No L3 cache misses at all, so it's bloody fast. Fun.
parity [...] BSR and BSF
You don't know what parity is, do you? POPCNT is halfway there, but you need a few more instructions. (Aside: When I last tried, common compilers still don't know how to use the sign flag correctly; try if((a + b) < 0), the expected result should be add followed by js/jns).
Everyone uses SSE/AVX
No, they shouldn't be except for the special purposes those instructions were designed for, i.e. applications that require lots of parallel operations on data. Video and image processing, mostly.
microcode execution engine which is very RISC like
It's not. This is marketing myth.
>>34 As if MIPS' completely separate result registers and arcane timing requirements are any better? And ARM didn't even have a divide instruction until very recently...
Neither did the Z80, which is why x86's divide is such a kludge. They kept the ugly divide which almost always needs a stack operation or register spill because of its unusual requirements. With register renaming there is no special accumulator, but people have to pretend it exists and make unnecessary memory writes. So what? If the language doesn't let you use the full functionality of the CPU then it's the language's fault.
It's computed with every single arithmetic instruction just to be thrown away. Why not add things to the CPU to help with languages instead of the other way around? Again, it's the compiler writers that need to get smarter. And if anything, stack-based ISAs are far easier to generate code for than register-based.
Automatic stacks are easier, not a fixed 8-item stack with manual management. Look at source for GCC, the JVM, or any other portable compiler. They have to add kludges for x87 compared to all other supported targets. So what?
Partial flags register updates, ADD and INC are different, SUB and DEC are different, and all of those other quirks, just because that's how the 8008/8080/Z80 did it. You get compilers that do add eax, 1 instead of inc eax to avoid a partial flags stall. So what? You get backwards compatibility for free, and can switch into protected mode if needed; it's only 4 instructions or so, and you get to decide what the GDT should be. Intel did try making a CPU that booted in protected mode, the 80376, and it failed miserably: you still needed to setup the protected mode stuff, and lost the ability to run existing code, so there was absolutely no advantage.
Intel/AMD dropped most of segmentation to phase out the "legacy" modes. If it still boots in real mode, they'll have to keep that stuff forever. Ever tried DOS benchmarks on a late-model i7? No L3 cache misses at all, so it's bloody fast. Fun.
It's fast, but you're only using 1/1000 of your RAM and have no hardware support (floppy disk and ISA cards are gone).
Name:
Anonymous2013-02-03 14:54
>>37
Don't try to seduce Cudder with your CPU bullshit, i saw her first.
Name:
Anonymous2013-02-03 16:13
BUT THE TPM USES ISA
ISA WAS JUST RENAMED LPC
ISA WILL NEVER DIE
YOU CAN TAKE MY CMOS FROM MY COLD DEAD HANDS
AS WELL AS MY NMI DISABLE PORT FUCKER
>>34
The 376 didn't fail because they eliminated real mode; it failed because it didn't have paging and thus remained incompatible with a garden variety 386 even after it had booted.
The embedded market has always been wary of Intel pushing weird crap, and history has consistently upheld their skepticism. You may point to the 386EX as a success story, but every ODM that went with that chip got burned because Intel was disinterested and provided no upgrade path for them.
make unnecessary memory writes.
If it's to the stack, they can be treated as registers; they're almost as fast due to store/load buffers.
It's computed with every single arithmetic instruction just to be thrown away.
It doesn't cost anything extra except <1K transistors on a chip with approximately 6 orders of magnitude more.
Why not add things to the CPU to help with languages instead of the other way around?
HLLs will never exploit the full functionality of the CPU.
Look at source for GCC, the JVM, or any other portable compiler. They have to add kludges for x87 compared to all other supported targets
So what? Every architecture is unique, that's what makes them special. A bounded stack isn't any more difficult to generate code for, unless the compiler writers were completely idiotic in their approach and tried to think of all architectures as the same... which they aren't. It's very easy to write a dumb compiler (see otcc, tcc); it's hard to write one that makes use of the architecture effectively.
ADD and INC are different, SUB and DEC are different[...]just because that's how the 8008/8080/Z80 did it
They had a very good reason to make them different, and in a very specific way. Hint: ADC, SBB.
You get compilers that do add eax, 1 instead of inc eax to avoid a partial flags stall.
A few extra cycles on Nehalem, which is NOTHING in comparison to the HUNDRED or more of a cache miss caused by larger code when there are many of those. Those extra cycles don't matter the majority of the time even if there isn't a cache miss, since these CPUs are superscalar and out-of-order; they'll just find some other instructions to execute in the meantime. The issue is pretty much gone in Sandy Bridge. Same for many other instructions that used to be slower, they've realised that fetch/decode bandwidth is important so they're working on making the instructions faster --- as they should be. They probably delay disclosing this information, but make the appropriate changes to their compiler, so they can stay ahead.
Someone from Intel talks about the block move instructions here, 6 years ago: http://software.intel.com/en-us/forums/topic/275765
and from what I've seen, they have managed to make MOVSD come out on top again starting with Nehalem, so now everything makes sense and there's no longer a need for bloated unrolled and aligned memcpy implementations when 2 bytes suffice. Aligned or not, rounded sizes or not, it's all done in hardware now. If my predictions are right, lods/stos may make a comeback too.
Intel/AMD dropped most of segmentation to phase out the "legacy" modes.
AMD did it, Intel had no intention to.
It's fast, but you're only using 1/1000 of your RAM and have no hardware support (floppy disk and ISA cards are gone).
Processing power and RAM are not necessarily correlated, some applications can benefit greatly from raw execution speed but don't need more than a few K of RAM, and others are the opposite. If you don't have an FDC then you bought the wrong mobo.
>>41 because it didn't have paging
Paging is useless for most embedded applications, which need guaranteed latency and may not even have mass storage to page to.
You may point to the 386EX as a success story, but every ODM that went with that chip got burned because Intel was disinterested and provided no upgrade path for them.
Ditto for the i860 and i960... and yet MCS-51 lives on.
tl;dr: While you academics are intellectually masturbating over impractical "elegant" architectures the real world has shown that a complex ISA is no obstacle to performance, quite the contrary as it allows for a lot of hardware optimisation, and as memory bandwidths become the bottleneck, dense CISC is the future.
IIRC it's only MMX and above that's the subject of patents (don't know when they'll expire, should go read up on them someday...); that's why DMP still makes 486-compatible SoCs (Vortex86).
tl;dr: While you academics are intellectually masturbating over impractical "elegant" architectures the real world has shown that a complex ISA is no obstacle to performance, quite the contrary as it allows for a lot of hardware optimisation, and as memory bandwidths become the bottleneck, dense CISC is the future.
Moron.
_____________
Posted from my MINIX box. Say no to Linux and BSD!
Name:
Anonymous2013-02-07 1:12
>>44
There's more to the MMU than that. Protection and address space virtualization are still useful even if you don't want deal with replacing pages on demand.
Also, it's obvious why the 8051 is still around: Intel no longer controls the ISA. With an 8051, you needn't worry about having your single source abandon you when their view of the market changes.
>>47
No citation or uname -a. And I have no idea why you have something against *BSD. MIMIX dev's and supporters are not.
>>49
Parallelism. And a RISC that deals with that, will be ahead of any CISC. Problem is, CISC's have already started first, and due to the massive instruction set, more reliable in the long run ofr dedicated programs.
>>48 Protection and address space virtualization are still useful even if you don't want deal with replacing pages on demand.
Segmentation works fine for that.
Also, it's obvious why the 8051 is still around: Intel no longer controls the ISA.
Nor do they need to, since the whole opcode space has been assigned already (except for one slot at A5, which has become de-facto standard for a debugging breakpoint.) 8051 is mature, finished, and stable. There's no need to change it; it's evolved to perfection for its application.
Parallelism. And a RISC that deals with that, will be ahead of any CISC.
Good luck finding enough memory bandwidth... CISC will always have the code density advantage. With cores these days running at several times memory speed, the bottleneck is not instruction decoding or execution, it's at the memory interface. It gets even worse with more cores.
CISC scales with hardware improvement because single instructions perform many operations, that although initially slow, can be improved by hardware. Something like add [ebx+esi*4+34], ax might've taken several dozen clock cycles before, but could take less than 1 in the future; and it's the same 5 bytes. Complexity in the instruction set is design that looks forward, building in anticipation for future improvements. The block move instruction I mentioned above is an excellent example; with a RISC ISA all you can do is code a loop, possibly a bloated unrolled one, and it's very difficult for the CPU to figure out that the series of instructions it's executing is a block move, and thus optimise it in hardware. It's easy to break complex instructions apart, it's harder to combine them together.
>>44 HLLs will never exploit the full functionality of the CPU.
That's a terrible justification for creating an ISA that's hard to write a code generator for. The vast majority of the code that runs on a given CPU is going to be written in a HLL. If you cannot provide an instruction set that compiler writers can easily use (or at least limit the ugly parts to application domains that favor a small ASM library), you have failed.
You can't fork or mmap with only a segmentation unit. And please don't say those operations aren't suitable for RTOS use when the most common RTOSes all provide a POSIX layer that uses them.
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Name:
Anonymous2013-02-07 21:47
>>52
x86 is a terrible CISC. Instructions that use specific registers and goofy encodings make things harder for compilers, assembly programmers, assembler writers, and techniques like register renaming. x86 is full of quirks like the segment descriptor format, the DIV instruction, multiple encodings for the SAME instruction using the direction bit, LAHF/SAHF to mimic the Z80's AF, and the immediate byte after AAM. CISC is about making the interface simpler than the implementation. With x86, the dividend must be loaded into eax/edx, the divisor must be in memory or a register, and the quotient is returned in eax. The VAX lets you use any addressing mode with any instruction, so there are instructions like divl3 #17, #400000, r2 which will store 23529 in r5. It's easier to remember, easier to program, and easier to compile to. RISC keeps the same idea, but instead of arbitrary addressing modes, it only allows registers.
Name:
Anonymous2013-02-07 22:11
>>62 BUT THE MICROARCHITECTURE OF MOST INTEL CPU'S SINCE P5 IS CISC UNDER THE 'HOOD'if you know what I mean
Name:
Anonymous2013-02-07 22:12
i meant risc 50KM SPREAD VAGINA WAITING, WAITING AND WANTING, FROTHINGLY FRESH
>>60
This is actually the first occurrence of ``Registers Innumerable, Shitty Cache'' on the Internet. I'm parroting your phrase so I may find it later with /prog/scrape.
That's a terrible justification for creating an ISA that's hard to write a code generator for. [...]If you cannot provide an instruction set that compiler writers can easily use
The hardware designers shouldn't be dumbing-down the ISA for stupid compiler writers. Perhaps I should say "misguided" and not "stupid", since the problem seems more that they are not approaching the task of code generation in the right way.
You can't fork or mmap with only a segmentation unit. And please don't say those operations aren't suitable for RTOS use when the most common RTOSes all provide a POSIX layer that uses them.
POSIX is NOT a good specification for RTOS as much as they try to make it one. It's far too heavyweight. True realtime systems often do not even have the concept of a "process", it is closer to threads. (A router running Linux or whatever doesn't count. Embedded != realtime.)
>>62 CISC is about making the interface simpler than the implementation
No, it's about code density and getting more work done per instruction. The VAX often gets mentioned for being "very CISC" bt actually doesn't have that great of a code density compared to x86, with the exception of certain very powerful instructions (but x86 also has things like AES, CRC, etc.) x86 was designed with code density in mind, so that the most common instructions are also the shortest. With the VAX, the 1-byte opcode map contains many of the "very CISC" instructions, like queue insert; this causes the most common instructions to need to be longer. In contrast, x86 puts the more powerful instructions on the 2nd or 3rd page, where they can still provide a gain in code density while not affecting the common ones.
E.g. what if the 1-byte move and 3-byte AES were exchanged? AES isn't done often, so the result is decreased code density since every move is now 2 bytes longer. AES still provides a gain since the equivalent sequence to emulate it would require many more bytes. This is why MMX, SSE, and all the newer stuff reside on the 2nd page --- although their opcodes are a bit longer, they are also less commonly used, and the operations they perform would still require many more bytes to implement if they weren't present.
So is x86 actually... okay? Is it actually better than I thought it was?
Name:
Anonymous2013-02-08 4:19
>>69
What do you mean by okay? Yes, it has legacy cruft in its architecture but we know it works and its practical to use for its purpose which is being the PC processor.
Name:
Anonymous2013-02-08 5:31
>>68
x86 demands constant register spill, by design, and you say the compiler writers are the stupid ones? Really? How much of your precious instruction density savings is spent by the additional instructions you must add to twiddle values about that tiny register set?
Name:
Anonymous2013-02-08 6:32
Are Intel just managing to polish turds in developing low-power processors?
>>71 register spill
That is a "RISCism", if you are thinking that way then you are not using x86 the way it was meant to be used. Most if not all operations can be register-memory, and the portion of memory around the stack pointer can be accessed basically at near-register speeds, so you can think of that as another few dozen 32-bit registers. EAX and EDX should be used for accumulation, EBX, ESI, and EDI pointers, and ECX loop counters.
How much of your precious instruction density savings is spent by the additional instructions you must add to twiddle values about that tiny register set?
Most register-register operations are 2 bytes, register-memory via [ebp+d8] is 3 bytes. If you need to do many operations in parallel then start considering MMX and SSE.
>>69
The CS academics love to bash it because they are abstractionists with their heads in the clouds and enjoy dreaming about "elegant" bullshit, while they complain about all the aspects of x86 they hate because they don't understand that those arose from practical considerations and just scream about it being too complex. Meanwhile the hardware designers have no problems with that complexity because it works well and they continue improving on the design by making it more complex. If you think x86 is ugly then you should think the same of the human genome, natural languages, or anything else that's evolved a long way; they're still around, because everything else failed.
>>73
The quirks in x86 make things harder for compilers, assembly programmers, debuggers, optimizers, OS developers, hardware designers, and hardware testers, and result in hardware that does less while using more power and transistors. Imagine if the billions of dollars that went into x86 instead went into a better architecture. Instead of instructions like DAA and LAHF (both one byte even though they're rarely used), there could be instructions that compilers can actually use. CALL instructions in x86 often need to be followed by a wasteful ADD to adjust the stack, which makes them longer than calls in RISCs. Branch-and-link is better for functional languages because it doesn't impose a stack. A conditional branch-and-link takes 4 bytes in RISC instruction sets. It's more general and more powerful, while also being shorter. Instead of looking at how the compiler can use instructions which ``arose from practical considerations'' in the 70's for Z80 compatibility, look at the types of instructions compilers need. Instead of having x87, MMX, and SSE with huge overlap in functionality, use a single vector/FP architecture.
An elegant instruction set makes for smaller compilers, easier debugging, easier assembly programming, and easier implementation. The last one seems to be the real reason for why Intel keeps pushing x86. Anyone can make a MIPS or ARM, but x86 has so many quirks and kludges that building it from scratch is almost impossible (not to mention that most of them will never be used). There are 4 security rings when everybody only uses 2, partial flag updates, ugly formats for internal structures, Task State Segments with limited hardware task switching, Call Gates, MSRs, SMM, irregular instructions (DIV, string instructions, so many others), encodable instructions that signal a GPF because they exceed 15 bytes, multiple prefixes with undefined behavior, and so many other ``features'' that it would take less time to design an instruction set and compiler than for a third party to implement x86 (even assuming they are able to license the patents from Intel).
Name:
Anonymous2013-02-08 15:32
>>68 The hardware designers shouldn't be dumbing-down the ISA for stupid compiler writers.
It's not ``dumbing-down the ISA'' because the x86 ISA already is dumb. What's dumb is having to push things onto the stack because operands need to be in certain registers. What's dumb is needing "instruction sequences" to do things that RISCs can do with single instructions. What's dumb is booting in 16-bit mode and having megabytes of firmware that can't be used after the boot process because they're still made for 16-bit OSes. What's dumb is still expecting software to fit the hardware even though all of Intel's attempts to do that (TSS task switch, 32-bit segmented mode, A20 line, lack of V86 in the 286) have failed. I find it easier to write assembly for ARM than for x86, but I guess it would be ``dumbing-down the ISA'' for stupid assembly programmers too. Hardware should be designed for the programmer, to fit the software, not the other way around. Why make programmers and compiler writers bend over backwards at Intel's whim? Perhaps I should say "misguided" and not "stupid", since the problem seems more that they are not approaching the task of code generation in the right way.
What is ``the right way''? Most CPUs have a flat register file and a separate flat register file for floating-point. x86 has quirky integer registers and a stack for floating-point. Do you mean that compilers should use a separate back-end for x86 just because Intel wants to pretend it still has an accumulator?
CALL instructions in x86 often need to be followed by a wasteful ADD to adjust the stack
Heard of retn?
A conditional branch-and-link takes 4 bytes in RISC instruction sets.
In WHICH instruction set? In 32-bit code a destination address is already 4 bytes.
x87, MMX, and SSE with huge overlap in functionality
They're not a "huge overlap" if you know how to use them well.
An elegant instruction set makes for smaller compilers, easier debugging, easier assembly programming, and easier implementation.
"Easier" means NOTHING except in tiny embedded systems and the like, if it doesn't have PERFORMANCE.
Anyone can make a MIPS or ARM
And that's what happened. But can they compete with x86 performance?
There are 4 security rings when everybody only uses 2
WRONG. "majority" != "everybody".
it would take less time to design an instruction set and compiler than for a third party to implement x86
Yes it would, but the performance of that instruction set and compiler would be, to use your colloquialisms, "shit". Not to mention being incompatible with most of the software ever written.
What's dumb is having to push things onto the stack because operands need to be in certain registers.
No, what's dumb is either you or the compiler, for not realising that beforehand and scheduling so the operands are in the right place at the right time.
having megabytes of firmware that can't be used after the boot process
Shows how much you know... real mode only has an address space of 1M and the real mode BIOS routines are a few hundred K at most, so your "megabytes of firmware" is total bullshit.
I find it easier to write assembly for ARM than for x86
Obviously because you don't know x86, you know ARM. Trying to write x86 Asm pretending the machine is like an ARM does not work well.
Hardware should be designed for the programmer, to fit the software, not the other way around
You cannot break the laws of physics. The hardware designers know more about that than programmers pretending to be hardware designers.
What is ``the right way''?
"It depends", but certainly thinking it is like any other general boring architecture is NOT the right way.
Most CPUs have a flat register file
Define "most" and "flat register file".
Do you mean that compilers should use a separate back-end for x86
They should have a separate one for each architecture they support. Each architecture is DIFFERENT. MIPS has no real r0, while there is on ARM. MIPS does not predicate, ARM can predicate almost all instructions. etc.
Intel wants to pretend it still has an accumulator?
Not "pretend", it IS the accumulator; there are short-form variants of many instructions when using it. A compiler, and whoever wrote it, who doesn't realise that the code generation should make use of this fact is just as stupid as one that doesn't make use of the fact that r0 is always zero on MIPS.
tl;dr: Don't understand x86 (or hardware in general), don't argue against it.
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Anonymous2013-02-09 9:41
>>77
WHAT >>74 IS FUCKING TELLING YOU is that there is REAL ESTATE on the chip supporting all that legacy SHITE that could either be DONE AWAY WITH, lowering the COST of the CPU, or used to say, add another CORE, or PIPELINE, or PCIE lane but instead it stays there, due the need for BACKWARDS COMPATIBILITY WITH ENTERPRISE ANUSES like a TUMOR
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Anonymous2013-02-09 10:36
>>78 all that legacy SHITE that could either be DONE AWAY WITH, lowering the COST of the CPU
What portion of the billion or two of the total number of transistors in a modern CPU are dedicated to the legacy shite and what kind of reduction in cost are you expecting?
As you can see, the areas of this single core chip that are consumed by INSTRUCTION DECODE and COMPLEX INSTRUCTION SUPPORT (I like to call that a crutch) are LARGE. As in ELEPHANT DICK LARGE.
If the instruction set were simpler, they could have
- saved power and money by not including it
- added more floating point pipelines
- enlarged the cache
- other shit
So this is P5. It's only gotten worse with additional shit added on since then. Multiply that by six, eight cores and WELL, WE CAN'T HAVE SOFTWARE DEVELOPERS LEARN NEW SHIT NOW.
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Anonymous2013-02-09 15:18
As in ELEPHANT DICK LARGE.
As in less than 10% of the total size? So if they threw out say half of the instruction set (being extremely generous here), the chip will be 5% cheaper and more energy efficient?
It's only gotten worse with additional shit added on since then.
I thought your problem was not with new useful shit but with useless legacy shit, the proportion of which decreased as more shit was added?
Also, original P5 had 3 million transistors, Sandy Bridge has about 250 millions per core, what does that say about the proportion of transistors wasted on legacy shit and the possibility for improvement by cutting it off?
I'm getting a feeling that you're a humanities major and a goy, to be honest. Your inability to intuitively grasp basic mathematical properties of the situation and the implications for possible efficiency and profit gains is hard to explain otherwise.
>>73
If hitting the stack frame was really so fast, all Intel's optimization guides wouldn't pointedly tell you to avoid it.
>>80,81
The power penalty to run that decoder is no more than 5% these days. Area cost is even smaller, and will continue to shrink.
Modern Intel CPUs will burn through a task and return to sleep faster than a similar ARM will, so the overall impact of the decoder is really, really insignificant. Intel knows its hardware to the exclusion of all else so they can easily justify keeping it this way.
Intel's real problems with low power are more diverse than the instruction set. For the longest time, they simply didn't want to compete in the market because the margins there are too low for them to sustain themselves. You don't get to keep running big expensive cutting-edge fab by selling cheap chips for mobile and embedded devices. Sour grapes, really.
Now Intel has no choice but to admit that ARM is cannibalizing their market from below, but they just don't have the expertise needed to integrate devices that anyone will buy. Their ODM partners are clueless and the market leaders have no interest in reaching out to them. Instead, they keep chasing process leads while all the designs that they need to get their foot in the door are still trending out 12-18 months...
>>79,81
Good to see someone else here with knowledge of how hardware works...
80386 1.5um process die. 275,000 transistors in 104mm2. Density of approximately 2.6K transistors/mm2.
8-core Xeon E5 (Sandy Bridge) 32nm process die. 2,270,000,000 transistors in 434mm2. Density of approximately 5.23M transistors/mm2.
The amount of chip area needed for an entire 386 in the 32nm process would be 0.05mm2, or about 0.23mm on a side. The Xeon E5 die is around 21mm on a side. That's an entire working 386, complete with all the "legacy" instructions and everything, and it takes only 0.01% of the die space in a modern processor, or around the same size as 4 bond pads.
That tiny square, a miniscule bit compared to the entire die which looks enormous in comparison; until you realise the die itself is only ~21mm square.
Would they remove that just for the sake of academic "elegance", at the HUGE cost of losing backwards compatibility?
Now Intel has no choice but to admit that ARM is cannibalizing their market from below
Intel actually has an ARM license. They don't intend to use it.
Medfield looks pretty good for a first try. Intel never cared much about low power, they were after performance first. But now that they're trying, it'll be interesting to see what happens. Having an entire PC-compatible smartphone would be awesome. ARM is only compatible at the ISA level, everything else is different (and difficult to find info on) between the SoCs.
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Anonymous2013-02-10 6:12
Stop! Cudder time!
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Anonymous2013-02-10 11:32
>>81, this is 80.
I believe I have learned something here, and was really just being silly. I do apologize.
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Anonymous2013-02-10 11:37
Cudder-sama, are you an electrical/electronic engineer? why do you know so much about hardware? ;_;
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Anonymous2013-02-10 11:45
>>87
Ever heard of those scary viruses and malwares made by evil russians? Well, that's Cudder.
>>84 Intel actually has an ARM license. They don't intend to use it.
That license is also old - they might have to shell out more money to get access to the newer stuff. Intel has plenty of money for that, of course, if they want it.
Medfield looks pretty good for a first try. Intel never cared much about low power, they were after performance first. But now that they're trying, it'll be interesting to see what happens. Having an entire PC-compatible smartphone would be awesome.
The Windows 8 boondoggle makes it pretty clear that the consumer mass market couldn't care less about Intel's cherished PC compatibility (and Medfield isn't PC compatible, anyway). The commercial embedded market, where such things have more weight, is already deeply distrustful of Intel and won't chase their offerings unless and until they demonstrate a clear price advantage. The continued investment in fab instead of buying their way back into the LTE market demonstrates to me that Intel would rather die than live on the ARM vendors' margins.
>>92 Medfield isn't PC compatible, anyway
Not fully (obviously it's going to lack things like an 8042 because the smartphone doesn't even have a keyboard, and other devices where the associated peripheral isn't present, and the BIOS is similarly cut down --- although AFAIK it still boots in realmode), but it's compatible enough for e.g. standard Windows EXEs to run in userspace.
and won't chase their offerings unless and until they demonstrate a clear price advantage
Intel is not trying to compete in the value segment; they're aiming for performance, which is what x86 has always been good at. Just as most of the low-end market is dominated by AMD, Intel wants to take the high end and leave the low end to ARM, MIPS, and the rest.
>>93
The shortsightedness in this is that, if Intel keeps doing what they're doing, the whole consumer market will end up inside that segment. Funnily enough the company that helped create the ``killer micros'' keeps looking more and more like DEC did in its final days.
>>93 performance, which is what x86 has always been good at.
wat.
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Anonymous2013-02-11 13:45
>>93 performance, which is what x86 has always been good at.
RISCs were much faster than x86 until Intel and AMD implemented micro-ops. ALPHA still beat x86 until the day it died.
>>95,96
I'm saying x86 has a lot of performance potential. They might not've been fast before but they can certainly take advantage of it going forward.
No MIPSes, Alphas, nor ARMs found in the results, so can't compare there. Maybe back in the early 90s RISC would've enabled higher clockspeeds since that was how they played the performance tradeoff, but post-Netburst we all know that other things come into play and you can't raise the clockspeed infinitely high no matter how "simple" you make the design.
>>112
Cudder's a tranny bro. Your derpina has a derpenis.
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1132013-02-12 3:04
I'm just wondering: have you guys ever craved cock so badly that you found yourself running around outside, howling at the moon for it? Literally ROARING at the top of your lungs, wanting nothing less than a dick's head churning against your glottal stop?
Tell me I'm not alone.
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Anonymous2013-02-12 4:05
No, I mena, Cudder is one of many [female] pseudonyms for a guy, not that many people are posting under that one pseudonym.