World's Thickest Book

Intel should publish all of their documentation, including

http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-manual-325462.html
and
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html

in one book.

>>52
x86 is a terrible CISC. Instructions that use specific registers and goofy encodings make things harder for compilers, assembly programmers, assembler writers, and techniques like register renaming. x86 is full of quirks like the segment descriptor format, the DIV instruction, multiple encodings for the SAME instruction using the direction bit, LAHF/SAHF to mimic the Z80's AF, and the immediate byte after AAM. CISC is about making the interface simpler than the implementation. With x86, the dividend must be loaded into eax/edx, the divisor must be in memory or a register, and the quotient is returned in eax. The VAX lets you use any addressing mode with any instruction, so there are instructions like divl3 #17, #400000, r2 which will store 23529 in r5. It's easier to remember, easier to program, and easier to compile to. RISC keeps the same idea, but instead of arbitrary addressing modes, it only allows registers.