CALL instructions in x86 often need to be followed by a wasteful ADD to adjust the stack
Heard of
ret n?
A conditional branch-and-link takes 4 bytes in RISC instruction sets.
In WHICH instruction set? In 32-bit code a destination address is already 4 bytes.
x87, MMX, and SSE with huge overlap in functionality
They're not a "huge overlap" if you know how to use them well.
An elegant instruction set makes for smaller compilers, easier debugging, easier assembly programming, and easier implementation.
"Easier" means NOTHING except in tiny embedded systems and the like, if it doesn't have PERFORMANCE.
Anyone can make a MIPS or ARM
And that's what happened. But can they compete with x86 performance?
There are 4 security rings when everybody only uses 2
WRONG. "majority" != "everybody".
partial flag updates
>>44
ugly formats for internal structures
Subjective.
it would take less time to design an instruction set and compiler than for a third party to implement x86
Yes it would, but the performance of that instruction set and compiler would be, to use your colloquialisms, "shit". Not to mention being incompatible with most of the software ever written.
What's dumb is having to push things onto the stack because operands need to be in certain registers.
No, what's dumb is either you or the compiler, for not realising that beforehand and scheduling so the operands are in the right place at the right time.
having megabytes of firmware that can't be used after the boot process
Shows how much you know... real mode only has an address space of 1M and the real mode BIOS routines are a few hundred K at most, so your "megabytes of firmware" is total
bullshit.
I find it easier to write assembly for ARM than for x86
Obviously because you don't know x86, you know ARM. Trying to write x86 Asm pretending the machine is like an ARM does not work well.
Hardware should be designed for the programmer, to fit the software, not the other way around
You cannot break the laws of physics. The hardware designers know more about that than programmers pretending to be hardware designers.
What is ``the right way''?
"It depends", but certainly thinking it is like any other general boring architecture is NOT the right way.
Most CPUs have a flat register file
Define "most" and "flat register file".
Do you mean that compilers should use a separate back-end for x86
They should have a separate one for each architecture they support. Each architecture is DIFFERENT. MIPS has no real r0, while there is on ARM. MIPS does not predicate, ARM can predicate almost all instructions. etc.
Intel wants to pretend it still has an accumulator?
Not "pretend", it IS the accumulator; there are short-form variants of many instructions when using it. A compiler, and whoever wrote it, who doesn't realise that the code generation should make use of this fact is just as stupid as one that doesn't make use of the fact that r0 is always zero on MIPS.
tl;dr: Don't understand x86 (or hardware in general), don't argue against it.