World's Thickest Book

Intel should publish all of their documentation, including

http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-manual-325462.html
and
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html

in one book.

>>34
The 376 didn't fail because they eliminated real mode; it failed because it didn't have paging and thus remained incompatible with a garden variety 386 even after it had booted.

The embedded market has always been wary of Intel pushing weird crap, and history has consistently upheld their skepticism. You may point to the 386EX as a success story, but every ODM that went with that chip got burned because Intel was disinterested and provided no upgrade path for them.

>>40
Use [m] you dumb fuck

                    __   __   __   __                                 __             __       
|     /\   |\/|    /__` /  \ |__) |__) \ /        |     /\   |\/|    |__) |     /\  /  ` |__/ 
|    /~~\  |  |    .__/ \__/ |  \ |  \  |  .      |    /~~\  |  |    |__) |___ /~~\ \__, |  \ .

make unnecessary memory writes.
If it's to the stack, they can be treated as registers; they're almost as fast due to store/load buffers.

It's computed with every single arithmetic instruction just to be thrown away.
It doesn't cost anything extra except <1K transistors on a chip with approximately 6 orders of magnitude more.

Why not add things to the CPU to help with languages instead of the other way around?
HLLs will never exploit the full functionality of the CPU.

Look at source for GCC, the JVM, or any other portable compiler. They have to add kludges for x87 compared to all other supported targets
So what? Every architecture is unique, that's what makes them special. A bounded stack isn't any more difficult to generate code for, unless the compiler writers were completely idiotic in their approach and tried to think of all architectures as the same... which they aren't. It's very easy to write a dumb compiler (see otcc, tcc); it's hard to write one that makes use of the architecture effectively.

ADD and INC are different, SUB and DEC are different[...]just because that's how the 8008/8080/Z80 did it
They had a very good reason to make them different, and in a very specific way. Hint: ADC, SBB.

You get compilers that do add eax, 1 instead of inc eax to avoid a partial flags stall.
A few extra cycles on Nehalem, which is NOTHING in comparison to the HUNDRED or more of a cache miss caused by larger code when there are many of those. Those extra cycles don't matter the majority of the time even if there isn't a cache miss, since these CPUs are superscalar and out-of-order; they'll just find some other instructions to execute in the meantime. The issue is pretty much gone in Sandy Bridge. Same for many other instructions that used to be slower, they've realised that fetch/decode bandwidth is important so they're working on making the instructions faster --- as they should be. They probably delay disclosing this information, but make the appropriate changes to their compiler, so they can stay ahead.

Someone from Intel talks about the block move instructions here, 6 years ago:
http://software.intel.com/en-us/forums/topic/275765
and from what I've seen, they have managed to make MOVSD come out on top again starting with Nehalem, so now everything makes sense and there's no longer a need for bloated unrolled and aligned memcpy implementations when 2 bytes suffice. Aligned or not, rounded sizes or not, it's all done in hardware now. If my predictions are right, lods/stos may make a comeback too.

Intel/AMD dropped most of segmentation to phase out the "legacy" modes.
AMD did it, Intel had no intention to.

It's fast, but you're only using 1/1000 of your RAM and have no hardware support (floppy disk and ISA cards are gone).
Processing power and RAM are not necessarily correlated, some applications can benefit greatly from raw execution speed but don't need more than a few K of RAM, and others are the opposite. If you don't have an FDC then you bought the wrong mobo.

>>41
because it didn't have paging
Paging is useless for most embedded applications, which need guaranteed latency and may not even have mass storage to page to.

You may point to the 386EX as a success story, but every ODM that went with that chip got burned because Intel was disinterested and provided no upgrade path for them.
Ditto for the i860 and i960... and yet MCS-51 lives on.


tl;dr: While you academics are intellectually masturbating over impractical "elegant" architectures the real world has shown that a complex ISA is no obstacle to performance, quite the contrary as it allows for a lot of hardware optimisation, and as memory bandwidths become the bottleneck, dense CISC is the future.

Cudder, I really think, the other person wants to say, that he just wants an open source CISC, that is not proprietary bound.

I just wonder how we will survive the parallelism crisis.

>>45
http://www.ht-lab.com/freecores/cpu8086/cpu86.html
http://zet.aluzina.org/index.php/Zet_processor
http://opencores.org/project,rtf8088

IIRC it's only MMX and above that's the subject of patents (don't know when they'll expire, should go read up on them someday...); that's why DMP still makes 486-compatible SoCs (Vortex86).

tl;dr: While you academics are intellectually masturbating over impractical "elegant" architectures the real world has shown that a complex ISA is no obstacle to performance, quite the contrary as it allows for a lot of hardware optimisation, and as memory bandwidths become the bottleneck, dense CISC is the future.
Moron.

_____________
Posted from my MINIX box. Say no to Linux and BSD!

>>44
There's more to the MMU than that. Protection and address space virtualization are still useful even if you don't want deal with replacing pages on demand.

Also, it's obvious why the 8051 is still around: Intel no longer controls the ISA. With an 8051, you needn't worry about having your single source abandon you when their view of the market changes.

RISC is the future. Deal with it you fucking CISC faggots.

I think Cudder has friendzoned me. ;_;

>>47
No citation or uname -a. And I have no idea why you have something against *BSD. MIMIX dev's and supporters are not.

>>49
Parallelism. And a RISC that deals with that, will be ahead of any CISC. Problem is, CISC's have already started first, and due to the massive instruction set, more reliable in the long run ofr dedicated programs.

999GFLOPS[i]![/!]

>>47
I think I've proved my point well enough. ;)

>>48
Protection and address space virtualization are still useful even if you don't want deal with replacing pages on demand.
Segmentation works fine for that.

Also, it's obvious why the 8051 is still around: Intel no longer controls the ISA.
Nor do they need to, since the whole opcode space has been assigned already (except for one slot at A5, which has become de-facto standard for a debugging breakpoint.) 8051 is mature,  finished, and stable. There's no need to change it; it's evolved to perfection for its application.

Parallelism. And a RISC that deals with that, will be ahead of any CISC.
Good luck finding enough memory bandwidth... CISC will always have the code density advantage. With cores these days running at several times memory speed, the bottleneck is not instruction decoding or execution, it's at the memory interface. It gets even worse with more cores.

CISC scales with hardware improvement because single instructions perform many operations, that although initially slow, can be improved by hardware. Something like add [ebx+esi*4+34], ax might've taken several dozen clock cycles before, but could take less than 1 in the future; and it's the same 5 bytes. Complexity in the instruction set is design that looks forward, building in anticipation for future improvements. The block move instruction I mentioned above is an excellent example; with a RISC ISA all you can do is code a loop, possibly a bloated unrolled one, and it's very difficult for the CPU to figure out that the series of instructions it's executing is a block move, and thus optimise it in hardware. It's easy to break complex instructions apart, it's harder to combine them together.

Here's something interesting:

Nehalem: LOOP 6uops, 4 clocks
Sandy Bridge: LOOP 7uops, 5 clocks
Bulldozer: LOOP 1uop, 1-2 clocks

Odd that AMD's optimisation guide is still recommending against it, when it's now become faster than dec/jz (1.5-2.5 clocks).

>>52
Problem is, CISC's have already started first, and due to the massive instruction set, more reliable in the long run for dedicated programs.

You can read sarcasm‽

>>53
no

>>44
HLLs will never exploit the full functionality of the CPU.

That's a terrible justification for creating an ISA that's hard to write a code generator for. The vast majority of the code that runs on a given CPU is going to be written in a HLL. If you cannot provide an instruction set that compiler writers can easily use (or at least limit the ugly parts to application domains that favor a small ASM library), you have failed.

>>52
Segmentation works fine for that.

You can't fork or mmap with only a segmentation unit. And please don't say those operations aren't suitable for RTOS use when the most common RTOSes all provide a POSIX layer that uses them.

Check your privilege, CISC scum.

>>56
die cisc scum

I'm laughing so hard right now.

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 Y88b    /  888     888  Y88b       /                                                                                   
  Y88b  /   888     888   Y88b  e  /                                                                                    
   Y888/    888     888    Y88bd8b/                                                                                     
    Y8/     888     888     Y88Y8Y                                                                                      
     Y      888____ 888      Y  Y                                                                                       
                                                                                                                        
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  Y88b/    e88~-888 "88_88" 888 888  888  e88~-888       888 888 8888    888Y88b   888 888  888 "88_88"       888  Y88b 
   Y8/    C888  888  /      888 888  888 C888  888       888 888 Y888    888 Y88b  888 888  888  /            888   888D
    Y      "88_-888 Cb      888 888  888  "88_-888       888 888  "88__/ 888  Y88b 888 888  888 Cb            888 \_88P 
                     Y8""8D                                                                      Y8""8D                 
                                       888                    88~\          888                                         
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  Y888/Y88b/   8888   | 888  888 8888  888 8888__888 888     888   888  888 888                                         
   Y8/  Y8/    Y888   ' 888  888 Y888  888 Y888    , 888     888   888  888 888                                         
    Y    Y      "88_-~  888  888  "88_/888  "88___/  888     888   "88_-888 888                                         
                                                                                                                        

   ____   ____  ____      ____                                                                                                   
  6MMMMb/ `MM' 6MMMMb\   6MMMMb/                                                                                                 
 8P    YM  MM 6M'    `  8P    YM                                                                                                 
6M      Y  MM MM       6M      Y                                                                                                 
MM         MM YM.      MM                                                                                                        
MM         MM  YMMMMb  MM                                                                                                        
MM         MM      `Mb MM                                                                                                        
MM         MM       MM MM                                                                                                        
YM      6  MM       MM YM      6                                                                                                 
 8b    d9  MM L    ,M9  8b    d9                                                                                                 
  YMMMM9  _MM_MYMMMM9    YMMMM9                                                                                                  
                                                                                                                                 
                                                                                                                                 
                                                                                                                                 
                                                                                                                                 
                                                                                                                                 
   ____                     68b             ____                        ___         ____  ___                           ___      
  6MMMMb/                   Y89             `MM'                        `MM        6MMMMb\`MM              68b          `MM      
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6M      Y    ___   ___  __  /  /M            MM ___  __   /M      ____   MM       MM       MM  __  ___  __ ___ ___  __   MM   __ 
MM         6MMMMb  `MM 6MMb   /MMMMM         MM `MM 6MMb /MMMMM  6MMMMb  MM       YM.      MM 6MMb `MM 6MM `MM `MM 6MMb  MM   d' 
MM        8M'  `Mb  MMM9 `Mb   MM            MM  MMM9 `Mb MM    6M'  `Mb MM        YMMMMb  MMM9 `Mb MM69 "  MM  MMM9 `Mb MM  d'  
MM            ,oMM  MM'   MM   MM            MM  MM'   MM MM    MM    MM MM            `Mb MM'   MM MM'     MM  MM'   MM MM d'   
MM        ,6MM9'MM  MM    MM   MM            MM  MM    MM MM    MMMMMMMM MM             MM MM    MM MM      MM  MM    MM MMdM.   
YM      6 MM'   MM  MM    MM   MM            MM  MM    MM MM    MM       MM             MM MM    MM MM      MM  MM    MM MMPYM.  
 8b    d9 MM.  ,MM  MM    MM   YM.  ,        MM  MM    MM YM.  ,YM    d9 MM       L    ,M9 MM    MM MM      MM  MM    MM MM  YM. 
  YMMMM9  `YMMM9'Yb_MM_  _MM_   YMMM9       _MM__MM_  _MM_ YMMM9 YMMMM9 _MM_      MYMMMM9 _MM_  _MM_MM_    _MM__MM_  _MM_MM_  YM._
                                                                                                                                 
                                                                                                                                 
                                                                                                                                 
                                                                                                                                 
                                                                                                                                 
        ___                            ____                          ___                                                         
        `MM      68b                  6MMMMb/                        `MM  6MMMb   6MMMb                                          
  /      MM      Y89                 8P    YM                         MM 6M' `Mb 6M' `Mb                                         
 /M      MM  __  ___   ____         6M      Y ___  __ ___   ___   ____MM `'   MM `'   MM                                         
/MMMMM   MM 6MMb `MM  6MMMMb\       MM        `MM 6MM `MM    MM  6MMMMMM      MM      MM                                         
 MM      MMM9 `Mb MM MM'    `       MM         MM69 "  MM    MM 6M'  `MM     ,M9     ,M9                                         
 MM      MM'   MM MM YM.            MM         MM'     MM    MM MM    MM    MM9     MM9                                          
 MM      MM    MM MM  YMMMMb        MM         MM      MM    MM MM    MM    M       M                                            
 MM      MM    MM MM      `Mb       YM      6  MM      MM    MM MM    MM                                                         
 YM.  ,  MM    MM MM L    ,MM        8b    d9  MM      YM.   MM YM.  ,MM   68b     68b                                           
  YMMM9 _MM_  _MM_MM_MYMMMM9          YMMMM9  _MM_      YMMM9MM_ YMMMMMM_  Y89     Y89                                           
                                                                                        

  ____  ___ ____   ____                                                                                 
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  ___) | | | | | |_| |_| |_| | | |__| (_| | (__| | | |  __/                                             
 |____/|_| |_|_|\__|\__|\__, |  \____\__,_|\___|_| |_|\___|                                             
                        |___/                                                                           

                                                                                                                  
MMM"""AMV `7MMF' .M"""bgd   .g8"""bgd                                                                             
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'   AMV     MM  `MMb.     dM'       `                                                                             
   AMV      MM    `YMMNq. MM                                                                                      
  AMV   ,   MM  .     `MM MM.                                                                                     
 AMV   ,M   MM  Mb     dM `Mb.     ,'                                                                             
AMVmmmmMM .JMML.P"Ybmmd"    `"bmmmd'                                                                              
                                                                                                                  
                                                                                                                  
                                                                                                                  
              ,,                                                         ,,                                       
`7MN.   `7MF' db                                  .M"""bgd mm          `7MM              `7MMM.     ,MMF'         
  MMN.    M                                      ,MI    "Y MM            MM                MMMb    dPMM           
  M YMb   M `7MM  .P"Ybmmm  .P"Ybmmm ,6"Yb.      `MMb.   mmMMmm ,pW"Wq.  MM  .gP"Ya        M YM   ,M MM `7M'   `MF'
  M  `MN. M   MM :MI  I8   :MI  I8  8)   MM        `YMMNq. MM  6W'   `Wb MM ,M'   Yb       M  Mb  M' MM   VA   ,V 
  M   `MM.M   MM  WmmmP"    WmmmP"   ,pm9MM      .     `MM MM  8M     M8 MM 8M""""""       M  YM.P'  MM    VA ,V  
  M     YMM   MM 8M        8M       8M   MM      Mb     dM MM  YA.   ,A9 MM YM.    ,       M  `YM'   MM     VVV   
.JML.    YM .JMML.YMMMMMb   YMMMMMb `Moo9^Yo.    P"Ybmmd"  `Mbmo`Ybmd9'.JMML.`Mbmmd'     .JML. `'  .JMML.   ,V    
                 6'     dP 6'     dP                                                                       ,V     
                 Ybmmmd'   Ybmmmd'                                                                      OOb"      
                                                                                                                  
                                                ,,                                                                
`7MM"""Yb.                                    `7MM                                                                
  MM    `Yb.                                    MM                                                                
  MM     `Mb  .gP"Ya   ,p6"bo   ,pW"Wq.    ,M""bMM  .gP"Ya `7Mb,od8                                               
  MM      MM ,M'   Yb 6M'  OO  6W'   `Wb ,AP    MM ,M'   Yb  MM' "'                                               
  MM     ,MP 8M"""""" 8M       8M     M8 8MI    MM 8M""""""  MM                                                   
  MM    ,dP' YM.    , YM.    , YA.   ,A9 `Mb    MM YM.    ,  MM                                                   
.JMMmmmdP'    `Mbmmd'  YMbmd'   `Ybmd9'   `Wbmd"MML.`Mbmmd'.JMML.                                                 
                                                                                                                  
                                                                                                                  

>>52
x86 is a terrible CISC. Instructions that use specific registers and goofy encodings make things harder for compilers, assembly programmers, assembler writers, and techniques like register renaming. x86 is full of quirks like the segment descriptor format, the DIV instruction, multiple encodings for the SAME instruction using the direction bit, LAHF/SAHF to mimic the Z80's AF, and the immediate byte after AAM. CISC is about making the interface simpler than the implementation. With x86, the dividend must be loaded into eax/edx, the divisor must be in memory or a register, and the quotient is returned in eax. The VAX lets you use any addressing mode with any instruction, so there are instructions like divl3 #17, #400000, r2 which will store 23529 in r5. It's easier to remember, easier to program, and easier to compile to. RISC keeps the same idea, but instead of arbitrary addressing modes, it only allows registers.

>>62
BUT THE MICROARCHITECTURE OF MOST INTEL CPU'S SINCE P5 IS CISC UNDER THE 'HOOD'if you know what I mean

i meant risc 50KM SPREAD VAGINA WAITING, WAITING AND WANTING, FROTHINGLY FRESH

       _..._                                                 _..._                                                                             
    .-'_..._''.                                           .-'_..._''.                                                                          
  .' .'      '.\    .                  __.....__        .' .'      '.\      .                     ,.--.         __.....__       __  __   ___   
 / .'             .'|              .-''         '.     / .'               .'|                    //    \    .-''         '.    |  |/  `.'   `. 
. '              <  |             /     .-''"'-.  `.  . '               .'  |                    \\    |   /     .-''"'-.  `.  |   .-.  .-.   '
| |               | |            /     /________\   \ | |              <    |                     `'-)/   /     /________\   \ |  |  |  |  |  |
| |               | | .'''-.     |                  | | |               |   | ____                  /'    |                  | |  |  |  |  |  |
. '               | |/.'''. \    \    .-------------' . '               |   | \ .'                        \    .-------------' |  |  |  |  |  |
 \ '.          .  |  /    | |     \    '-.____...---.  \ '.          .  |   |/  .                          \    '-.____...---. |  |  |  |  |  |
  '. `._____.-'/  | |     | |      `.             .'    '. `._____.-'/  |    /\  \                          `.             .'  |__|  |__|  |__|
    `-.______ /   | |     | |        `''-...... -'        `-.______ /   |   |  \  \                           `''-...... -'                    
             `    | '.    | '.                                     `    '    \  \  \                                                           
                  '---'   '---'                                        '------'  '---'                                                         

>>59-61
Excellent shitposting, keep it up man.

>>65
You're supposed to do that only when the last two digits of your posts coincide.  Didn't they teach you about 'dubz' in shitposting university?

>>60
This is actually the first occurrence of ``Registers Innumerable, Shitty Cache'' on the Internet.  I'm parroting your phrase so I may find it later with /prog/scrape.

That's a terrible justification for creating an ISA that's hard to write a code generator for. [...]If you cannot provide an instruction set that compiler writers can easily use
The hardware designers shouldn't be dumbing-down the ISA for stupid compiler writers. Perhaps I should say "misguided" and not "stupid", since the problem seems more that they are not approaching the task of code generation in the right way.

You can't fork or mmap with only a segmentation unit. And please don't say those operations aren't suitable for RTOS use when the most common RTOSes all provide a POSIX layer that uses them.
POSIX is NOT a good specification for RTOS as much as they try to make it one. It's far too heavyweight. True realtime systems often do not even have the concept of a "process", it is closer to threads. (A router running Linux or whatever doesn't count. Embedded != realtime.)

>>62
CISC is about making the interface simpler than the implementation
No, it's about code density and getting more work done per instruction. The VAX often gets mentioned for being "very CISC" bt actually doesn't have that great of a code density compared to x86, with the exception of certain very powerful instructions (but x86 also has things like AES, CRC, etc.) x86 was designed with code density in mind, so that the most common instructions are also the shortest. With the VAX, the 1-byte opcode map contains many of the "very CISC" instructions, like queue insert; this causes the most common instructions to need to be longer. In contrast, x86 puts the more powerful instructions on the 2nd or 3rd page, where they can still provide a gain in code density while not affecting the common ones.

E.g. what if the 1-byte move and 3-byte AES were exchanged? AES isn't done often, so the result is decreased code density since every move is now 2 bytes longer. AES still provides a gain since the equivalent sequence to emulate it would require many more bytes. This is why MMX, SSE, and all the newer stuff reside on the 2nd page --- although their opcodes are a bit longer, they are also less commonly used, and the operations they perform would still require many more bytes to implement if they weren't present.

So is x86 actually... okay? Is it actually better than I thought it was?

>>69
What do you mean by okay? Yes, it has legacy cruft in its architecture but we know it works and its practical to use for its purpose which is being the PC processor.

>>68
x86 demands constant register spill, by design, and you say the compiler writers are the stupid ones? Really? How much of your precious instruction density savings is spent by the additional instructions you must add to twiddle values about that tiny register set?

Are Intel just managing to polish turds in developing low-power processors?

>>71
register spill
That is a "RISCism", if you are thinking that way then you are not using x86 the way it was meant to be used. Most if not all operations can be register-memory, and the portion of memory around the stack pointer can be accessed basically at near-register speeds, so you can think of that as another few dozen 32-bit registers. EAX and EDX should be used for accumulation, EBX, ESI, and EDI pointers, and ECX loop counters.

How much of your precious instruction density savings is spent by the additional instructions you must add to twiddle values about that tiny register set?
Most register-register operations are 2 bytes, register-memory via [ebp+d8] is 3 bytes. If you need to do many operations in parallel then start considering MMX and SSE.

>>69
The CS academics love to bash it because they are abstractionists with their heads in the clouds and enjoy dreaming about "elegant" bullshit, while they complain about all the aspects of x86 they hate because they don't understand that those arose from practical considerations and just scream about it being too complex. Meanwhile the hardware designers have no problems with that complexity because it works well and they continue improving on the design by making it more complex. If you think x86 is ugly then you should think the same of the human genome, natural languages, or anything else that's evolved a long way; they're still around, because everything else failed.

http://yarchive.net/comp/linux/x86.html

>>73
The quirks in x86 make things harder for compilers, assembly programmers, debuggers, optimizers, OS developers, hardware designers, and hardware testers, and result in hardware that does less while using more power and transistors. Imagine if the billions of dollars that went into x86 instead went into a better architecture. Instead of instructions like DAA and LAHF (both one byte even though they're rarely used), there could be instructions that compilers can actually use. CALL instructions in x86 often need to be followed by a wasteful ADD to adjust the stack, which makes them longer than calls in RISCs. Branch-and-link is better for functional languages because it doesn't impose a stack. A conditional branch-and-link takes 4 bytes in RISC instruction sets. It's more general and more powerful, while also being shorter. Instead of looking at how the compiler can use instructions which ``arose from practical considerations'' in the 70's for Z80 compatibility, look at the types of instructions compilers need. Instead of having x87, MMX, and SSE with huge overlap in functionality, use a single vector/FP architecture.

An elegant instruction set makes for smaller compilers, easier debugging, easier assembly programming, and easier implementation. The last one seems to be the real reason for why Intel keeps pushing x86. Anyone can make a MIPS or ARM, but x86 has so many quirks and kludges that building it from scratch is almost impossible (not to mention that most of them will never be used). There are 4 security rings when everybody only uses 2, partial flag updates, ugly formats for internal structures, Task State Segments with limited hardware task switching, Call Gates, MSRs, SMM, irregular instructions (DIV, string instructions, so many others), encodable instructions that signal a GPF because they exceed 15 bytes, multiple prefixes with undefined behavior, and so many other ``features'' that it would take less time to design an instruction set and compiler than for a third party to implement x86 (even assuming they are able to license the patents from Intel).

>>68
The hardware designers shouldn't be dumbing-down the ISA for stupid compiler writers.
It's not ``dumbing-down the ISA'' because the x86 ISA already is dumb. What's dumb is having to push things onto the stack because operands need to be in certain registers. What's dumb is needing "instruction sequences" to do things that RISCs can do with single instructions. What's dumb is booting in 16-bit mode and having megabytes of firmware that can't be used after the boot process because they're still made for 16-bit OSes. What's dumb is still expecting software to fit the hardware even though all of Intel's attempts to do that (TSS task switch, 32-bit segmented mode, A20 line, lack of V86 in the 286) have failed. I find it easier to write assembly for ARM than for x86, but I guess it would be ``dumbing-down the ISA'' for stupid assembly programmers too. Hardware should be designed for the programmer, to fit the software, not the other way around. Why make programmers and compiler writers bend over backwards at Intel's whim?
Perhaps I should say "misguided" and not "stupid", since the problem seems more that they are not approaching the task of code generation in the right way.
What is ``the right way''? Most CPUs have a flat register file and a separate flat register file for floating-point. x86 has quirky integer registers and a stack for floating-point. Do you mean that compilers should use a separate back-end for x86 just because Intel wants to pretend it still has an accumulator?

>>74
I read was blah blah blah. For a change, make your own CPU aligned with your ideals. Waiting to see it at opencores.org

>>75
Same thing with >>74, the answer is, make your own CPU with your aligned language. Tell me how that works out.

CALL instructions in x86 often need to be followed by a wasteful ADD to adjust the stack
Heard of ret n?

A conditional branch-and-link takes 4 bytes in RISC instruction sets.
In WHICH instruction set? In 32-bit code a destination address is already 4 bytes.

x87, MMX, and SSE with huge overlap in functionality
They're not a "huge overlap" if you know how to use them well.

An elegant instruction set makes for smaller compilers, easier debugging, easier assembly programming, and easier implementation.
"Easier" means NOTHING except in tiny embedded systems and the like, if it doesn't have PERFORMANCE.

Anyone can make a MIPS or ARM
And that's what happened. But can they compete with x86 performance?

There are 4 security rings when everybody only uses 2
WRONG. "majority" != "everybody".

partial flag updates
>>44

ugly formats for internal structures
Subjective.

it would take less time to design an instruction set and compiler than for a third party to implement x86
Yes it would, but the performance of that instruction set and compiler would be, to use your colloquialisms, "shit". Not to mention being incompatible with most of the software ever written.

What's dumb is having to push things onto the stack because operands need to be in certain registers.
No, what's dumb is either you or the compiler, for not realising that beforehand and scheduling so the operands are in the right place at the right time.

having megabytes of firmware that can't be used after the boot process
Shows how much you know... real mode only has an address space of 1M and the real mode BIOS routines are a few hundred K at most, so your "megabytes of firmware" is total bullshit.

I find it easier to write assembly for ARM than for x86
Obviously because you don't know x86, you know ARM. Trying to write x86 Asm pretending the machine is like an ARM does not work well.

Hardware should be designed for the programmer, to fit the software, not the other way around
You cannot break the laws of physics. The hardware designers know more about that than programmers pretending to be hardware designers.

What is ``the right way''?
"It depends", but certainly thinking it is like any other general boring architecture is NOT the right way.

Most CPUs have a flat register file
Define "most" and "flat register file".

Do you mean that compilers should use a separate back-end for x86
They should have a separate one for each architecture they support. Each architecture is DIFFERENT. MIPS has no real r0, while there is on ARM. MIPS does not predicate, ARM can predicate almost all instructions. etc.

Intel wants to pretend it still has an accumulator?
Not "pretend", it IS the accumulator; there are short-form variants of many instructions when using it. A compiler, and whoever wrote it, who doesn't realise that the code generation should make use of this fact is just as stupid as one that doesn't make use of the fact that r0 is always zero on MIPS.

tl;dr: Don't understand x86 (or hardware in general), don't argue against it.

>>77

WHAT >>74 IS FUCKING TELLING YOU is that there is REAL ESTATE on the chip supporting all that legacy SHITE that could either be DONE AWAY WITH, lowering the COST of the CPU, or used to say, add another CORE, or PIPELINE, or PCIE lane but instead it stays there, due the need for BACKWARDS COMPATIBILITY WITH ENTERPRISE ANUSES like a TUMOR

>>78
all that legacy SHITE that could either be DONE AWAY WITH, lowering the COST of the CPU
What portion of the billion or two of the total number of transistors in a modern CPU are dedicated to the legacy shite and what kind of reduction in cost are you expecting?

Here's a simple example from the original Pentium:
http://www.computerhistory.org/timeline/images/1993_intel_pentium_large.jpg

As you can see, the areas of this single core chip that are consumed by INSTRUCTION DECODE and COMPLEX INSTRUCTION SUPPORT (I like to call that a crutch) are LARGE.  As in ELEPHANT DICK LARGE.

If the instruction set were simpler, they could have

- saved power and money by not including it
- added more floating point pipelines
- enlarged the cache
- other shit

So this is P5.  It's only gotten worse with additional shit added on since then.  Multiply that by six, eight cores and WELL, WE CAN'T HAVE SOFTWARE DEVELOPERS LEARN NEW SHIT NOW.