looking to see if you champions have any opinions on either.
i'm most likely going to teach myself verilog because i'm more familiar with c style syntax and my professor recommended it.
Learn to do it by hand first. This includes learning an assembly language. Your colleagues will hate you if you treat Verilog like Java without any understanding of the underlying mechanisms.
Never use a language until you know what it's doing. The same holds true for C, as you probably don't know.
Hay guyz, some months ago there was a tremendously wankery thread over how terrible PDFs are (OH SHI- can of worms) and how blah blah blah octet-streams, but as an example, someone linked to a site with searchable research papers from all kinds of disciplines as an example of why PDFs are actually good.
I wish I could still find it; does anyone know what I'm talking about?
Scheme is a statically scoped and properly tail-recursive dialect of the Lisp programming language invented by Guy Lewis Steele Jr. and Gerald Jay Sussman
>>13
Witless ape, when compelled to smear fæces upon your face and swing them at passers-by, indulge in a minute of reflection to contemplate the potential results of your actions.
Kindest regards,
ANUSLORD
Name:
Anonymous2011-03-17 15:14
From what I've read, there's a difference in U.S. vs. Europe - the U.S. largely uses Verilog, while Europe largely uses VHDL.
I've only used VHDL myself, and it's verbose as fuck. I assume Verilog is a bit more hacky.
A simple counter in VHDL:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity counter is
generic( SIZE : natural := 10 );
port( clock : in std_logic;
rst : in std_logic;
value : out unsigned(SIZE - 1 downto 0) );
end counter;
architecture behavioral of counter is
signal value_s: unsigned(SIZE - 1 downto 0);
begin
value <= value_s;
process(clock)
begin
if rising_edge(clock) then
-- synchronous active high reset. Asynchronous active low resets are preferable on some technologies.
if rst = '1' then
value_s <= (others => '0');
else
value_s <= value_s + 1;
end if;
end process;
end architecture behavioral;
>>77
I learned monads and I implemented them in Scheme, still I'd never learn Haskell.
Python sucks by itself, you don't need to hate it for the FIOC, I agree.
I learned VHDL, but I have to say it's very verbose and Pascal-ish for me (long keywords, usually unneeded). There are some features which make VHDL better sematically than Verilog (I don't know enough Verilog to tell if Verilog doesn't have equivalent features for those things. I'm considering learning Verilog some days as it seems to have slightly less verbose syntax. If I was actually in this business, I'd be more inclined to make something like I said in >>17