verilog vs vhdl

looking to see if you champions have any opinions on either.
i'm most likely going to teach myself verilog because i'm more familiar with c style syntax and my professor recommended it.

inb4 verilog is the future or learn both

also if you're up for it, gimme any tips you got.

I learned VHDL, but I have to say it's very verbose and Pascal-ish for me (long keywords, usually unneeded). There are some features which make VHDL better sematically than Verilog (I don't know enough Verilog to tell if Verilog doesn't have equivalent features for those things. I'm considering learning Verilog some days as it seems to have slightly less verbose syntax. If I was actually in this business, I'd be more inclined to make something like I said in >>17