verilog vs vhdl

looking to see if you champions have any opinions on either.
i'm most likely going to teach myself verilog because i'm more familiar with c style syntax and my professor recommended it.

inb4 verilog is the future or learn both

also if you're up for it, gimme any tips you got.

From what I've read, there's a difference in U.S. vs. Europe - the U.S. largely uses Verilog, while Europe largely uses VHDL.

I've only used VHDL myself, and it's verbose as fuck. I assume Verilog is a bit more hacky.

A simple counter in VHDL:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity counter is
  generic( SIZE : natural := 10 );
  port( clock : in  std_logic;
        rst :   in  std_logic;
        value : out unsigned(SIZE - 1 downto 0) );
end counter;

architecture behavioral of counter is
  signal value_s: unsigned(SIZE - 1 downto 0);
begin
  value <= value_s;

  process(clock)
  begin
    if rising_edge(clock) then
      -- synchronous active high reset. Asynchronous active low resets are preferable on some technologies.
      if rst = '1' then
        value_s <= (others => '0');
      else
        value_s <= value_s + 1;
    end if;
  end process;
end architecture behavioral;