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Instruction Set Micro-Optimizations

Name: Anonymous 2012-11-28 18:01

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

Name: Anonymous 2012-11-29 12:52

>>19
ARM has the load multiple/store multiple instructions that do exactly that. I assume they're not so common because they add complexity to exception handling. If an interrupt is triggered while the instruction is executing, do you delay the interrupt or do you add logic to make it interruptible? What if the instruction triggers a fault?

>>22
In the original implementations, the zero register would have been implemented as a physically read-only register which doesn't need special handling. It's still faster than spending an instruction clearing a register.

>>21
Hennessy & Patterson, "Computer Architecture: A Quantitative Approach" (usually just referred to as "Hennessy & Patterson") is the SICP of computer architecture (except it's actually both good and relevant). If you need something more introductory, the same authors have another book, "Computer Organization and Design" (referred to as "Patterson & Hennessy" to avoid confusion between the two). Stallings' "Computer Organization & Architecture" is another common introduction textbook. There's many more, but those are the ones I've read.

Once you've understood the basic theory, just download and read the architecture manuals for different processors. Most manufacturers make them available free of charge. If you can find places where actual chip architects hang out (instead of the usual /prog/rider "experts") it's worth hanging around. The comp.sys.arch newsgroup used to have lots of interesting discussions, not so much anymore. The Real World Tech website seems OK.

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