Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

I just remembered an interesting idea in the HuC6280 (6502 derivative used in the Hudson PC-Engine): It had 8 bank switching registers, and special instructions to transfer data between them and the accumulator. Rather than them being the expected "load from bank register #0, store in bank register #7" instructions, they treated the second byte of the instruction as a bitflag of registers to use; eg, "store the contents of the accumulator in bank registers #0, #1, and #2" if the byte was 0x07.

It wasn't actually that useful for bank switching, but it seems like a really good idea for stack operations! Instead of picking between "push register #x" and "push all registers," you could push and pop a series of registers with a simple bitflag, allowing you to, say, efficiently push only the registers that a subroutine or syscall will trash.

I'm not aware of any architectures that implement this type of stack operation, though. Strange, as it seems like it would be really useful alongside the simpler push single register instructions.