Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

>>16
fixed-sized instructions make instruction sequencing simpler
Yet, in this day and age, I think increasing complexity in the instruction sequencer would be justified if it lessened the burden on the instruction cache.

I'm also not buying the idea that minimizing the opcode field size so much (to the point of implementing register to register move with add 0, for example) actually makes efficient/powerful implementations any easier, since you have to "detect" all these special cases to avoid tying up the ALU for a stage in the pipeline actually computing add 0.

>>17,18
Yes yes, we're all aware of DMA constant fill operations. There are uses for load/store 0 or a dedicated zero register beyond filling swaths of memory, please read the thread.