Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

>>9
Other sources implement reg-reg move using add instead of or, but I don't know which one or indeed either is canonical. The book "See MIPS Run" (2nd ed) has an instruction table that includes pseudo-ops and their expansions, you should be able to find a pdf by Googling.

3-operand instructions are supposedly easier to generate code for. Fixed-size instructions make instruction sequencing simpler and thus require fewer transistors, which was one of the driving goals behind early RISC design (especially MIPS, which is also why the instruction set doesn't have redundancies).

>>10
A bit of an overgeneralization. Eg. SH has fixed 16-bit instructions.

The current trend is towards mixed-length instructions, but driven by code size for embedded microcontrollers rather than bandwidth reasons. ARM created Thumb-2, MIPS copied it as microMIPS.