Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

>>4
I get that, but I was having trouble coming up with actual uses for it. The only other one I could think of was adding a carry in bignum arithmetic with adc 0.

>>5,8
Thanks for these, I knew I was forgetting some tricks. Surprised that move between registers is implemented with or, though I suppose it's not too difficult to detect that a move is intended there.
Any other instances where a zero reg could be used to implement pseudoinstructions?

In more modern times, though, it seems to me that dedicated instructions would make it slightly easier to detect dependencies (essential for stuffing pipelines and advanced branch prediction).

I suppose the ultimate question is whether "dyadic" architectures (2 operands, one of which is also the destination) with more space in the instruction for opcodes, or "triadic" architectures (2 operands, separate destination) with less space for opcodes are superior for code density etc.

That, and variable width instructions vs. fixed width ones. When I look at the MIPS architecture instruction set, a lot of times it seems to me as if they were at a loss as to what to put into the remaining space in their instructions, like the shift amount in R instructions. Same with condition codes in ARM.