Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

You can synthesize some instructions using the zero register, eg. to negate a value you subtract from zero. Comparison instructions can be implemented using subtraction with the zero register as destination, discarding the results but keeping the status flags.

Zero is such a common operand value that it's a clear advantage to have a dedicated register on register-rich load-store arcitectures (eg. MIPS, POWER). Architectures with fewer registers usually don't have one (eg. ARM, SH) but for instance the MSP430 has a couple of constant generator registers that can create the most common constant values.

Two real-world MIPS examples: The move d, s pseudo-op is actually implemented as or d, s, $zero, and the unconditional branch b addr pseudo-op is implemented using a conditional branch instruction as beq $zero, $zero, offset.