Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

This thread is amateur level.

On a lot of architectures, the DMA controllers of memory buses can be programmed to flood fill huge pages of memory with zero values, circumventing the CPU cache and running in parallel of the CPU. The DMA controller can then trigger a hardware interrupt once the operation is complete.

Doing this stuff usually requires ring 0 privileges, so it's a technique more for OS, systems or device driver authors.

>>17
Also, I forgot to mention that on architectures with virtual memory, usually when an application allocates a block of pages, the memory pages are zero filled. The way it's usually done is to set all of the pages to the same zero-filled physical page. Reading is not an issue, but on write, a software interrupt is triggered which causes the OS to change to the actual physical page that was reserved in the original allocation.

http://en.wikipedia.org/wiki/Zero-copy