>>21
I've been working on one for over a year now, in the little spare time I have.
>>23
Beauty is in the eye of the beholder. All the RISCs I've seen are boring and restricted.
>>30
x86 isn't going away any time soon. None of the popular RISCs can consistently beat it in terms of software support, code density, and IPC. I've mentioned this before, clockspeeds and caches have physical limits on how big they can get. Things like bloated fixed-width instructions may be fast to decode, but waste bus and memory bandwidth --- and that's where the bottleneck is. In contrast if your instruction decoder is wide enough then it does not need to be clocked at such a high speed as the ALU and other computational units and can do more stuff in parallel. The RISC model requires that
everything go fast from the ALU to the RAM, with CISC (internally RISC-like) the CPU can run much faster without being starved by waiting for the memory.