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verilog help

Name: Anonymous 2012-04-20 18:11

Hey folks. I'm not comfortable in verilog and would appreciate any help or hints anyone could supply for my computer architecture homework assignment.

http://www.cs.unca.edu/~bruce/Spring12/320/Homework9.pdf

when she says "Write a program" am I suppose to make a separate module? Or augment the processor.v file like the extra credit problems? Thanks.

Name: Anonymous 2012-04-20 18:14

Ask your fucking TA. That's what they're for.

Name: Anonymous 2012-04-20 18:16

don't have a TA. but thanks for the advice.

Name: Anonymous 2012-04-20 18:17

i thought this was a forum to discuss programming. is this not an appropriate place to ask for advice?

Name: Anonymous 2012-04-20 20:00

>>4
read SICP

Name: Anonymous 2012-04-20 23:45

>>4
>>3
>>1
People here have a very autistic anally retentive mentality toward this board. All they do is cry about how bad the board is and how they can't discuss anything related to programming and then when someone tries to, you get posts like >>2 and >>5 and they continue to wonder why the board has these characteristics it sees as problematic.

Anyways I've never heard of verilog and I do not into adobe. Please tell your techer to use a plain text format for his shit like every sensible programmer does or I will do unfucking speakable things to him and everyone he has EVER, FUCKING, KNOWN.

Name: bampu pantsu 2012-05-29 4:32

bampu pantsu

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