Name: Anonymous 2012-04-20 18:11
Hey folks. I'm not comfortable in verilog and would appreciate any help or hints anyone could supply for my computer architecture homework assignment.
http://www.cs.unca.edu/~bruce/Spring12/320/Homework9.pdf
when she says "Write a program" am I suppose to make a separate module? Or augment the processor.v file like the extra credit problems? Thanks.
http://www.cs.unca.edu/~bruce/Spring12/320/Homework9.pdf
when she says "Write a program" am I suppose to make a separate module? Or augment the processor.v file like the extra credit problems? Thanks.