RISC

/prog/, I'm working on a RISC instruction set that is more RISC than any RISC out there. I've devised an instruction format, plus fifteen core instructions that should suffice for any programming out there. The instruction format, instruction forms, and instructions can be found here:

http://jsbin.com/ekuwap

Any comments or suggestions?

>>84
When I wrote "memory that doesn't exist" I was referring to the truly nonexistent parts of the memory address space, which have no hardware on the bus to respond to.

>>85
To be complete, the whole family of shift/rotates is
* left shift 0-pad
* right shift 0-pad
* left shift 1-pad (not as useful but included for completeness)
* right shift 1-pad (aka "arithmetic"/sign-preserving shift)
* left rotate
* right rotate
* left rotate through carry
* right rotate through carry
...which is conveniently encoded in 3 bits.

That also raises another point: Your CPU is missing multiple-precision arithmetic (ADC/SBC) instructions.