1.1 To familiarize with typical in-circuit emulation features.
1.2 Develop necessary skills to design, develop and test a 68000-based microcomputer system with the help of the PC-based MICE-III emulator.
2. LABORATORY
Computer Laboratory
3. EQUIPMENT
Description Quantity
IBM Compatible PC 2
MICE III In-Circuit Emulator System 1
MEX68KECB Educational Computer Board 1
HP54645A Digital Storage Oscilloscope (DSO) 1
Power Supply Unit 1
MV68K Emulator System Driver Software 1
Multi-meter 1
Kermit Communication Software 1
4. INTRODUCTION
An in-circuit emulator (ICE) is a hardware device used to debug the software of an embedded system or system under development as they usually lack keyboards, screens, and other helpful user interfaces.
The basic idea of an "in-circuit emulator" is that it provides an interface into the embedded system. The programmer uses the emulator to load programs into the embedded system, run them, step through them slowly, and see and change the data used by the system's software. ICE's are always tools that attach a terminal or PC to the embedded system. The terminal or PC provides an interactive user interface for the programmer to investigate and control the embedded system.
The term "emulator" is so named as its function is to "emulate" the central processing unit of the embedded system's computer. Often, it literally has a plug that plugs into the same socket as the CPU chip. Emulating the main computer lets it do anything that the main computer can do, but under the control of a programmer.
ICE is an indispensable tool for embedded system development. Without an ICE, the development of embedded systems can be extremely difficult, because there is usually no way to tell what went wrong. With an ICE, the programmer can usually test pieces of code, then isolate the fault to a particular failing piece of code, and then inspect the failing code and rewrite it to solve the problem.
Most ICEs consist of an adaptor unit that sits between the ICE host computer and the system to be tested. A header and cable assembly connects the adaptor to a socket where the actual CPU or microcontroller mounts within the embedded system. Recent ICEs enable a programmer to access the On-chip debug circuit which is integrated into CPU via JTAG in order to debug the software of an embedded systems.
The ICE emulates the CPU. From the system's point of view, it has a real processor fitted. From the programmer's point of view, the system under test is under full control, allowing the developer to load, debug and test code directly. Hence ICE provides the ability to integrate hardware and software development during all phases of the development cycle. The software designer should thus be able to work with the prototype hardware to verify the code to reduce the development time. In addition, the hardware engineer is able to construct the necessary hardware modules and test for conectness with simple test routines, thereby facilitating rapid debug process as the hardware modules are being developed.
The 68000 Educational Computer Board as the target system. A target system is a system under development. Normally, this will include the prototype on a breadboard, wire-wrapping board, or a PCB. The experiment is divided into two sections. The first section focuses on using the emulator to verify and debug on the hardware design. In section two, are steps to debug software by executing it in real-time.
5. EXPERIMENT
In this session you will learn to use the "MICE-III In-Circuit Emulator". Please pay attention to all the features provided on the MICE-III, as you will be heavily relying on the MICE-III to debug and verify most of the hardware and software modules developed by you during subsequent laboratory sessions.
The following tutorial has been prepared to assist you with this hands-on session. Please go through the tutorial below carefully and pay attention to the mini exercises stated there in.
5.1 MICE-III IN-CIRCUIT EMULATOR
5.1.1 Setup
The Motorola Education Computer Board (ECB) is hooked up as the target system, the microprocessor-based system we assume that you wish to test. Verify that the 68000 microprocessor chip of the ECB is removed from it's socket and replaced with the emulator's probe tip connecting the pod cable. Also, the emulator is connected to the PC's RS232-C serial communication port one via the computer port.
5.1.2 Normal Startup
Power up the ECB first followed by Emulator and then the PC. The system configuration is shown in Fig 1.1.
Host PC 1 Power Supply PC 2
|
Via Computer Port Via port 1
___________________ Emulator 68000 ____________ Type
MICE III ECB KERMIT
Double click
MICE III
Figure 1.1: System Configuration.
Emulator software (mv68k.exe) is provided for the host PC to communicate with the emulator. It resides in the sub-directory c: \mv68k. Follow the steps given below to
execute this driver software.
I. Double click the MICE-III icon made available on the WIN-95 screen
II. The emulator software will perform a self-test. Once this is over, the prompt '>' will appear. This will be referred to as the MICE-III command prompt from now onwards.
III. Should there be any errors, check to ensure that the power supply is switched on and connected to the ECB. Then, exit from the emulator software by entering the command 'ctrl-c' and re-start mv68k once again.
5.2 HARDWARE DEBUGGING
An emulator can be used to verify that "your" hardware design is error-free. The software engineer's model of the hardware design is reflected through the memory map of the system, e.g. Table 1.1 for the case of ECB.
A memory map is a table that shows the range of addresses that are made available to the programmer as memory and memory mapped I/O spaces. Only the proper bus connections and address decoding will result in the memory map as expected.
The emulator provides a feature to allocate memory area within the target system's memory map so that certain operations could be carried out during debugging. This process is termed as overlaying. Hence the term overlay memory. Once defined, the MICE-III will use the overlay memory whenever the CPU performs an access to this memory space. Note that the CPU is unaware of this as the MICE-III is capable of performing the necessary switching in real-time. We will demonstrate a use for this later when S/W debugging is carried out.
To clear any overlay memory (i.e. to map all the memory to the target system), enter
>MAP All E // The 'E' here means external memory
To verify it is mapped correctly, enter
>MAP
To configure that the DTACK* signal is generated externally, enter
>READY E
5.2.1 TESTING THE TARGET SYSTEM'S (ECB 'S) MEMORY
At any stage, you may press the 'ESC' key to exit to MICE-III prompt
5.2.1.1 System Memory
To display a block of memory block, enter
>MEMORY 0 20 (displays memory from location 0 to location 32)
[Note that the default base system for all numbers is hexadecimal. So, the 20 above is $20 = 32]
5.2.1.2 System Scratchpad Memory
To examine memory contents, enter the following:
>MEMORY 400 (displays 256 bytes ofmemory at a time)
You will note from the memory map of the ECB (Table 1.1 pg 9) that user memory is defined to exist between $900-$7FFF. This memory space could be verified by first writing and then by performing a read operation. Use the following commands in the order shown to carry out the user RAM testing process. (Note that you will be following the procedure explained in this section to test memory units developed, at a later stage, as part of your design exercise).
To check the existence of user memory, enter
>MEMORY 900 7FFF <Return> (refer to the memory map of the ECB)
Press the space bar for continuous display
Enter following to check the user memory a page at a time.
>MEMORY 900
To fill a block of memory with 55(hex), enter
>FILL900 7FFF 55
To verify that the memory is modified correctly, enter
>MEMORY 900 7FFF (Note: Use the 'ESC' key to abort the display)
Repeat the above operation with the byte pattern 'AA'. (Assess code 'A' → 41)
To store 55 into even and AA into odd locations of the memory block, enter
>SIZE WORD
>FILL 900 7F FF 55 AA
To store the string "HELLO "from address location 900, enter
>SIZE BYTE
>FILL 900 904 "HELLO"
To verify, enter
>MEMORY 900 904 (You may also use >MEMORY 900 LENGTH 4)
5.2.2 Read Only Memory (EPROM)
The TUTOR firmware is located at the EPROM address $8000 to $0BFFF. EPROM chips are normally not used during the early stages of a typical microprocessor-based system development exercise. One of the main reasons is that the use of EPROM programmers to store the program prior to testing can be very tedious and time consuming.
With the help of MICE-III, it is possible to develop and debug the software using its overlay memory. In other words, you can configure a part of the emulator's overlay memory to take up the EPROM 's place. Since the overlay memory is essentially a RAM, programs can be loaded with ease and tested. Once it is error free, you can transfer it into EPROM chips using an EPROM programmer.
The ECB's TUTOR firmware starts from location $8146. Since the memory locations contain machine codes (instructions), the display obtained using the MEMORY command will not be useful. Instead, you may use the DIS command to disassemble the codes. To disassemble the TUTOR firmware, enter
>DIS 8146
Although you are unlikely to interpret its purpose, you should nevertheless be able to verify that they are indeed 68000 assembly codes.
To verify that the EPROM locations cannot be modified without overlaying its memory space, follow the instructions below.
Attempt to modify the EPROM locations by entering
>FILL 8000 81FF 00
To check if any changes have been made to the EPROM locations, enter
>DIS 8146
5.2.3 Reset Vector
The first four words starting at address $000000 contains the reset exception vector. However, in the ECB, the reset vector is stored in the EPROM locations $8000-$8007. This means that whenever the CPU attempts to read from locations 0 to 7, EPROM locations $8000 to $8007 are selected to allow for the reset vectors to reside in the non-volatile (i.e. EPROM) memory space.
Note: The first four bytes (0 to 3) contain the address of the supervisory stack pointer (SSP) while the next four bytes contain the value of the program counter (PC).
To verify that the effect of reading from locations 0 to 7 and from 8000 to 8007 is the same, enter
>MEMORY 0 7
>MEMORY 8000 8007
5.2.4 Unused Memory Locations
The 68000 MPU can address up to sixteen megabytes of memory space. Not all systems fully occupy this space. Typically, there will be some "gap " in the memory map reflecting the unused memory locations. If memory device are not present, you will not be able to read from or write to them successfully. Verify that there are no devices unintentionally occupying these addresses. Memory read failure refers to a memory read operation whilst Memory write failure refers to memory write operation.
To examine the typical responses when unused memory locations are accessed, enter the following.
Interpret the above commands and confirm that the outcomes are as expected by referring to the memory map of the ECB (Table 1.1) and the MICE-III/IIIS 68K Series User's Guide manuals.
5.2.5 Input-Output Devices
"The ECB under test uses two MC6850 ACIAs (Asynchronous Communication Interface Adapters) and one MC68230 PI/T. ACIAs are chips that supports serial interface. An ACIA occupies two memory locations, but actually contains four registers: two read-only registers (status register and receive data register) and two write-only registers (control register and transmit data register). The first ACIA occupies the following two locations:-
Action Taken Register Accessed
Read from $10040 Status register
Write to $10040 Control register
Read from $10042 Receive data register
Write to $10042 Transmit data register
The ACTA can be used to transmit and receive characters serially. Writing a control byte into its control register programs it for a particular mode of operation. This is a one-time operation. When a character must be sent out through the ACIA say to a terminal display unit, it is simply written into the transmit data register. Similarly, any character that has arrived into the ACIA, say from a keyboard, it could be retrieved by reading its receive data register.
In the experiment, the PC2 (see figure 1.1) is connected to the serial port 1 of the ECB, by executing the KERMIT communication software on PC2.
Type the following commands on the second PC to establish the connection:
C:\Users >Kermit
Kermit-MS >set baud 9600
Ke1mit-MS >set port 2
Kermit-MS >connect
The terminal is now ready to communicate with the ECB 's serial port one. (If you are using the DATAMINI system as the second PC, then double click the 'Kermit'
(To exit from KERMIT, press 'ALT X or CTRL C ')
5.2.5.1 Transmitter and Receiver Setup for the ACIA
The ACIA must be initialized before use by programming the control register. Store $15 to the control register to setup the ACIA for 9600 baud, 8 data bit, 1 stop bit, no parity check. If you wish to know how this value was arrived at, you may refer to the ACIA data sheets. Please note that you are not expected to understand the operational details of the ACIA yet, but to learn how to verify the basic operation of an I/O device by performing read and write operations to its registers with the help of ICE.
To reset the ACIA and to store $15 into its control register, enter
>BYTE 10040 03
>BYTE 10040 15
Note that the ACIA's control and status registers use the same address location. They are differentiated only by the read and write operations (i.e. a write to 10040 accesses the control register while a read from 10040 accesses the status register).
To verify that what was written into the control register cannot be read back, enter
>MEMORY 10040 LENGTH 1
5.2.5.2 Transmitter Operation
A character can now be transmitted by transferring the ASCII equivalent code to the transmit data register of the ACIA (i.e. a write to location $10042). Any eiTor in transmission could be observed by examining the status register (i.e. by reading and interpreting the status register in location $10040).
To transmit ASCII code '31' (i.e. the number 1), enter
>Byte 10042 31
The number '1' should appear on the second PC's screen.
Noting that the ACIA is able to transmit one character at a time, try and send the word 'hello' to the PC screen (refer to Figure 1.2--ASCII character set).
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5.2.5.3 Receiver Operation
When a character is typed on the keyboard of the PC2 (see figure 1.1), it is transmitted to the ECB's serial port automatically. To test whether the receiver is working correctly, first type 'a' on the second PC's keyboard and then verify that it has been received correctly by reading the location 10042 as shown below.
>MEMORY 10042
Method to repeatedly read the receive data register of the ACIA
The following steps show how the macro feature available on MICE-III could be used to enable this repeated read operation.
At the MICE-III command prompt (i.e.'>' ), enter
>DOS
C:\mv68K> edit C:\users\ACIA.INC ;(create an include file called ACIA.INC)
Once you are in the editor environment, enter
:Loop
Memory 10042 length 4
Goto Loop
Now, save and exit from the editor. Then enter
C:\mv68K>EXIT ; (this will get you back to the MICE-III command prompt)
Now, enter
>INCLUDE C:\users\ACIA.INC
Now, press keys on the second PC's keyboard and observe the values read from location $10042.
5.3. SOFTWARE DEBUGGING
Designing and debugging software for microprocessor-based systems can benefit a lot from the presence of an In-Circuit Emulator (ICE). You can now debug software by executing it (in real-time) on the actual target hardware. In this section of the experiment, you will use some of these software tools to develop an assembly language program, download it to the target system and debug it using the event monitoring system of the emulator. You are encouraged to refer to the manuals for further information.
5.3.1 Program Development
The following 68000-assembly code is kept in "C:\USERS\move.asm" so that you need not spend time re-typing it. Study the operational details of this program (shown below).
To confirm it is present in C:\users\move.asm, enter
>DOS
>CD\USERS
>TYPE move.asm
*move.asrn
ORG $0
DC.L $00000444
DC.L $00008000
DC.L
ORG $900 Start of user RAM
SOURCE: DC.B 'THE QUICK BROWN FOX JUMPED OVER A LAZY DOG'
ORG $1000
DESTIN: DS.B 140
ORG $8000 Start of ROM
START: MOVE.L #42,D0 No. of bytes to move
MOVE.L #SOURCE,A0 source address
MOVE.L #DESTIN,A1 Destination address
MORE: MOVE.B (A0)+,D1 Copy one byte at a time
MOVE.B D1, (A1) +
DBEQ D0,MORE More to rnove?
SETUP: MOVE.L #$50,D0 Init counter
MOVE.L #$AA,D2 Pattern to fill
FILL: MOVE.B D2, (A1) + Fill one byte
DBEQ D0, FILL More to fill?
ETER: JMP ETER Eternal loop
END START
Assembling process:
>DOS
C:\Users>x68k move.asm
Linking Process:
C:\Users>link -c move.obj
This will generate a motorola S28 output file : move.s28
To return to MICE-III command prompt, enter
C:\users>EXIT
5.3.2 Testing the S/W
There are two possible ways to proceed with this. One could choose to transfer the contents of the move.hex into the EPROM chips with the help of an EPROM programmer. Once programmed, the EPROMs can be plugged into their respective places and hope that the S/W would run error free (which is very unlikely).
The second option, which is very attractive, is to set up the overlay memory on the MICE-III as an EPROM space and transfer the contents of the file move.s28 onto to this overlay EPROM location. Once transferred (down-loaded), the program can be tested in real-time. If errors exist, it can be single-stepped and break points could be added to support the debugging process. The modified code can then be transferred to the overlay memory space for further testing.
5.3.2.1 Overlay Memory Set-up
To overlay ECB's EPROM space, follow the steps shown below:
To set-up EPROM space as overlay memory space, enter
>MAP 8000 BFFF 1 1
To verify the modified memory map, enter
>MAP
From now onwards, the ECB's EPROM space is ignored and any accesses to this region of memory will select the overlay memory. This overlay memory resides within MICE-III.
To verify that the ECB's EPROM space is not accessible any more, enter
>MEMORY 8000
>DISASSEMBLE 8146
Note that since the ECB's firmware is not stored in the overlay memory, the CPU can no longer access the ECB's firmware stored in its EPROM space.
5.3.2.2 Initializing the reset vector
The reset vector must be initialized before the program could be executed, i.e. the reset vectors have to be loaded in memory location 0 to 7. Since the ECB 's EPROM space has been disabled, it becomes necessary to overlay memory locations 0 to 7 as well. Once this is done, the reset vector can be modified to allow the CPU to execute the program move.28, which is being kept in the EPROM' s overlay memory space.
Note: The minimum block size of the overlay memory definable on the MICE-III is 4K bytes. This implies that even though we require only the first eight locations to be overlaid, we must assign the first 4K bytes of the ECB's EPROM space as a minimum.
To map first 4KB starting from $0 as overlay memory,
>MAP 0 FFF 1 1
>MAP
To confirm that this range of memory could be modified, enter
>FILL 0 FFF 00
>MEMORY 0
The reset vector can now be modified to facilitate the execution of the program (i.e. move.s28). The next step is to down load the move.s28 file.
To down-load move.s28 into the overlay memory, enter
>DOWNLOAD move.s28
To verify that the s/w has been successfully downloaded into the overlay memory space, enter
>DISASSEMBLE 8000
>MEMORY 900
>MEMORY 1000
Now, load reset vector into the 68000 registers using the following command:
>RESET (Note that this command essentially copies the two long words that are kept in locations 0-7 into SSP and PC)
To confirm that the reset vector has been loaded successfully, enter
>REGISTER
Use the register view port to examine the PC and SSP values.
5.3.2.3 Executing your program
Now you are ready to execute the program, all you need to do is enter,
>GO (you may also type GO FROM 8000)
You will need to press the 'ESC' key to stop the program.
5.3.4 Single Stepping Your Program
Most, if not all programs will not execute correctly as expected the first time. You will need to use various debugging aids to fix both hardware and software bugs. Some of these aids include single stepping, setting breakpoints, etc. Sometimes when a program does not seem to do what it is supposed to do. You may have to single step through every instruction by issuing the STEP command. At each step, examine relevant register or memory contents in order to vetify the program logic.
To examine affected register/memory contents and PC after each step, enter
>RESET
>STEP (alternatively, you can press the F8 key)
Proceed to the remaining set of exercises only if you have become familiar with the basic features of ICE.
The following exercises are optional
5.3.5 Using Breakpoint
If a program is very lengthy, single stepping may be practically impossible. Breakpoint allows you to break into a program execution at a critical point, such as a branching instruction or return from a subroutine, so that you can examine register or memory contents to verify program logic and conectness. Breakpoint is one of the features provided by MICE-III emulator's event monitoring system. It has a total of 6 programmable events to support break points:
a) Events 1 and 2 are for real-time bus breakpoints.
b) Event 3 is for external h/w breakpoint.
c) Events 4, 5 and 6 are for execution breakpoints.
5.3.5.1 Simple Address Breakpoint
Exercise 1
Set a breakpoint at the MOVE instruction at SETUP label so that you can break in to check whether the DESTIN string is copied successfully by the MORE loop.
Procedure
To check for any existing event specifications, enter
>EVENT
To clear all existing event specifications, enter EVENT CLEAR
To set up the address breakpoint using address comparator 1, enter
>EVENT 4 8016
To display the modified event specification(s), enter
>EVENT
(Alternatively you can use the mouse to click on the corresponding instruction on the screen).
Break point setup process is now complete. The program can now be run-to break point once we initialize the memory locations and load the reset vector.
To initialize the target string area of memory and to re-load the reset vector, enter
>FILL 1000 10FF 00
>MEMORY 1000 10FF
>RESET
To run with breakpoint enabled, enter
>GO
To verify memory contents have been modified as expected, enter
>MEMORY 1000
Exercise 2
Type in the following commands to set up an EVENT 1 break point
Interpret what happens when the above commands are executed.
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6. APPENDIX
Experiment 1
Preparatory work to be completed before Session 2
1. Interface the RAM memory modules using pre-supplied address decoder circuitry. You are expected to adhere to the colour code (red for Vcc, black for ground, white for address, yellow for data and blue for control) when wire-wrapping the memory interface circuitry. Do not have wires on top of ICs as that restrict you from changing spoilt ICs easily.
2. Wire-wrap the ACIA interface circuitry and develop suitable methods to configure and test the serial port with ICE. You must take note that the requirements of the synchronous bus transfers are different. For example , they rely on the E-clock and uses synchronous bus transfer. Hence the VPA * signal is used instead of the DTACK* signal to indicate the synchronous transfer requirement. Sketch your interface in the log book.
3. Incorporate a suitable DTACK* generation circuitry for the RAM and ROM to ensure that the asynchronous transfer is terminated appropriately during each cycle and that only valid memory locations are accessed. Sketch your interface in the log book.
4. Establish suitable methods to initialize and configure the ACIA using ICE. You are encouraged to come up with your own demo to show that the ACIA is working well.
Note that a minimum address space of 2 bytes is required for the ACIA, 32-byte wide contiguous space for PI/T, and 16K bytes (8K words) for SRAM.
On the basis of the address decoding circuitry that has been set up for you, draw a memory map for your system, similar to the one shown for the ECB.
Note that only the address, data and power supply lines are connected to the memory modules. You are required to generate the necessary control signals for the memory modules (shown next to the relevant memory ICs on the TDB) using the address decoder O/P and 68000's control signals.
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No. 2 : Memory and Serial Port Design
Experiment 2: MEMORY AND SERIAL PORT DESIGN
1. OBJECTIVES
1.1 To interface and test the memory modules available on the TDB using MICE-III.
1.2 To configure and test the serial port interface.
2. LABORATORY
Computer Laboratory
3. EQUIPMENT
Description Quantity
IBM Compatible PC 2
MICE III In-Circuit Emulator System 1
Target Development Board 1
HP54645A Digital Storage Oscilloscope (DSO) 1
Power Supply Unit 1
MV68K Emulator System Driver Software 1
Multi-meter 1
Kermit Communication Software 1
4. INTRODUCTION
In this experiment, you are expected to verify that the memory modules (RAM) are fully functional. You may need to refer to the appropriate sections of the emulator in order to identify suitable methods to test these memory modules.
Note that only the address, data and power supply lines are connected to the memory modules. You are required to generate the necessary control signals for the memory modules (shown next to the relevant memory ICs on the TDB) using the address decoder o/p and 68000 ' s control signals.
You are also expected to ensure that the CLK and RESET signals of the 68000 fully comply with the technical specifications.
You must use this session to become familiar with the design of an RS-232 standard based serial port for a 68000 based system using the popular MC6850 Asynchronous Communications Interface Adapter (ACIA) IC. The 6850 and support ICs (MC 14411 , 74LS151 and MAX233) have been made available on the Target Development Board (TDB) . The necessary connections to the relevant pins of these ICs have been made available on the TDB. Note that the power supply lines have been connected to all the ICs associated with the ACIA circuitry. If you are required to use auto-vectored interrupt for the ACIA, you should wire-wrap your system accordingly.
5. EXPERIMENT
5.1 TESTING OF RAM MODULE
1. Perform tests (i.e. with the help of MICE-III) to verify that the address decode unit is fully functional and that the necessary CS* signals are generated as expected
Two possible methods for testing the address decoder unit are given below.
METHOD-A
a) Connect one of the CS * to the oscilloscope and configure it to perform a single sweep.
b) Then, perform a read from an appropriate address location using MICE-III's 'MEMORY' command.
c) Repeat the above steps to verify a11 the CS* signals to each memory module.
d) Observe the DTACK* signal with the oscilloscope and record it into your log book.
METHOD-B
(Attempt this method only if you are unable to obtained the CS* on the oscilloscope)
The MICE-III could also be made to perform repeated read from an address location in real time. This could be achieved by using the in-line assembler feature as follows:
>MAP 0 FFF 1 1
>ASSEMBLE 100
move.b #33 , 2000 ;move hexadecimal value 33 to location 2000 (hex).
bra 100
Now the above code could be made to execute in real time and the steps for this are as follows :
>REGISTER PC 100
>GO ;(press the 'ESC' key to stop the program)
This option would be preferable if the various stages of the CS * generation circuitry require examination with the help of an oscilloscope.
2. Refer to the methods used to test the ECB's memory units and apply these to test the memory modules (8K words of SRAM) available on the TDB. Once the memory modules are functional, prepare a suitable code to verify the entire memory space in real time.
3. This part of the experiment deals with the design of the serial port.
1.1 Ensure that the following steps have been completed prior to testing the serial interface:
1.1.1 The appropriate data bus (upper or lower byte) for interfacing the 6850' s data bus has been selected for communication between the 68000 and the ACIA.
1.1.2 The necessary logic to generate the ACIA_CS* signal has been implemented and that the CS0, CS1 , and CS2 of the ACIA are connected as required.
1.1.3 The rest of the signals such as the E-clock and address A1 have been supplied to the ACIA. Do not attempt to incorporate the interrupt circuitry until the basic ACIA interface is fully functional.
1.1.4 The MC14411 Bit-Rate Generator has been configured to provide a suitable clock rate to the ACIA ' s RXC1k and TXC1k inputs. The 74LS151 IC has been provided for s/w configurable baud rate generation and you may ignore this for the time being.
1.1.5 Transmit and receive data lines to the RS-232 port have been made via the MAX233 IC and that the CTS * and DCD* signals have been assigned to appropriate logic levels.
1.2 Refer to the MICE-III emulator exercise hand-out (i.e. Session 1 ) and run KERMIT on the second PC so that it could be used to test the TDB ' s serial port. Using MICE-III, initialize and configure the TDB's ACIA for communication. The control register must be loaded with $ 15 for proper communication with the PC terminal. Transmit and receive characters to fully test the TDB 's serial interface. Refer to the in-circuit emulator exercise for details on how to test the serial interface. Explain what is observed at the transmit and receive pins of the RS-232 port using the oscilloscope when you type some characters at the second PC.
1.3 Connect the transmit data pin of the ACIA to one of the oscilloscope' s channels . Observe the output pattern generated when a character is written into the ACIA ' s transmit data register and confirm that it is as expected. Also examine how the MAX233 IC modifies this pattem. Similarly, observe the pattems generated when a key is pressed on the second PC.
1.4 You may wish to write a small assembly program that polls the ACIA for a character and echoes it back to the terminal. This will be able to demonstrate that you can receive and transmit data.
The following exercises are optional
You are also expected to ensure that the CLK and RESET signals of the 68000 fully comply with the technical specifications . Confirm that the CLK and RESET signals applied to the MC68000 meets its specifications .
CLK Signal Generation
Connect the CLK signal (available on the TDB) to the DSO and measure the high/low times and the rise/fall times (Motorola's clock specifications are given in the CPE206/SC206 Data Reference Manual).
6. APPENDIX
Preparatory work to be completed before Session 3
Construct the MC68230 PI/T based printer interface on the TDB using the wirewrapping method. You are expected to adhere to the colour code (red-Vcc, black-ground, address-white, data-yellow, control-blue) when wire-wrapping the memory interface circuitry. All the necessary signals such as the lower address lines (A1 to A5), CLK, R/W*, data lines (either lower or upper), etc. can be obtained from the TDB 's bus connectors. Use the most appropriate output from the address decode unit to generate the PI/T' s CS* signal. Refer to page 680 of Clements[ 1 ] and wire-wrap the Centronics printer interface. Sketch your interface in the log book.
Identify the steps required to initialize the PI/T and develop suitable steps to facilitate the printing of a character. You must be clear about the handshake and other modes of operations chosen for this purpose. If necessary, refer to the S/W listing on page 681 of Clements[ l ]. In your logbook, write out the initialization sequence and pseudocode for printing characters to the printer. This will assist you in the actual testing during the session. You must arrive at the next laboratory session (session 3) with a pre-wired Centronics printer port interface.
Reference: Clements [ 1 ], Alan Clements, "Microprocessor Systems Design" , 3rd edition, PWS Publishing company.
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No. 3: Centronics Printer Port
Experiment 3: CENTRONICS PRINTER PORT
1. OBJECTIVES
Experiment 3
To verify that the MC68230 PI/T based Centronics printer port is fully functional .
2. LABORATORY
Computer Laboratory
3. EQUIPMENT
Desctiption Quantity
IBM Compatible PC 2
MICE III In-Circuit Emulator System 1
Target Development Board 1
HP54645A Digital Storage Oscilloscope (DSO) 1
Power Supply Unit 1
MV68K Emulator System Driver Software 1
Multi-meter 1
Kermit Communication Software 1
4. INTRODUCTION
This exercise aims to familiarize the students with Centronics printer port design for a 68000-based microcomputer system. The highly versatile MC68230 PI/T has been chosen to facilitate this interface with minimal hardware and software overheads. The parallel data link must conform to the Centronics standard, which is composed of an 8-bit data bus together with printer and data flow control signals.
The MICE-III In-Circuit Emulator should be used to debug and verify the printer interface. The Centronics port' s specifications and the method of configuring the PI/T could be obtained from the recommended text.
5. EXPERIMENT
5.1 Centronics printer Port Interface
In this lab session you will be expected to carrying out the necessary tests on the 68230 PI/T based printer port interface.
1 . Ensure that the following steps have been completed prior to testing the centronics port.
a) Choose either the upper or the lower data bus for interfacing the PI/T' s data bus to the 68000 and connect them up accordingly. Choose the appropriate upper or lower bus if you need to connect the PI/T for interrupt purposes.
b) Combine the address decoder output and necessary control signals to generate the PI/T_CS* signal. Ensure that the lower order address lines, DTACK* signals are connected as required.
c) Interface the PI/T ' s chosen port pins and its handshake signals to the Centronics port, paying attention to the interface requirements. Ensure that the data buffer is enabled and that the direction control is assigned correctly.
2. Perform suitable tests to confirm that the PI/T' s CS* signal is present. Next, check to see if you are able to successfully alter one of the internal registers of the PI/T.
3. Configure the PI/T for double buffered pulsed handshake mode of operation. Connect the printer to the Centronics port. Note that the handshake pins must be enabled only at the very end of the initialisation sequence.
4. Write a value into the port data register and verify that it could be printed successfully.
5. Develop a suitable assembly routine to print a character string to the printer.
NOTES:
The MICE-III can be used to configure the PI/T and transmit characters for printing.
6. APPENDIX
Preparatory work to be completed before Session 4
You are required to study the online reference material for the Renesas H8-38086 microcontroller. For those of you who do not have any experience with 'C' programming language, you are required to refer to the online reference materials. Please also attempt to run the blinking LED program provide with the H8-38086 CPU board and be familiar with the HEW software development environment.
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No. 4: High-Performance Embedded Workshop (HEW) Exercise and Timer Based LED Module
Experiment 4: HIGH-PERFORMANCE EMBEDDED WORKSHOP (HEW) EXERCISE AND TIMER BASED LED MODULE
1 . OBJECTIVES
1.1 To familiarize with the High-performance Embedded Workshop (HEW) development environment,
1.2 Develop necessary skills to design, develop and test a H8/H8S-based microcontroller system using embedded 'C' language,
1.3 To configure and test the timer unit for controlling the brightness of the LED.
2. LABORATORY
Computer Laboratory
3. EQUIPMENT
Description Quantity
IBM Compatible PC 2
High-performance Embedded Workshop version 4.0 1
H8-38086 CPU board 1
HP54645A Digital Storage Oscilloscope (DSO) 1
Power Supply Unit 1
Multi-meter 1
4. INTRODUCTION
The High-performance Embedded Workshop (HEW) is the software development platform for Renesas series of microcomputer. It has a fully comprehensive development environment incorporating the compiler, assembler, linker and debugger to facilitate an integrated platform for software development. The primary software is embedded C/C++, however, the user has the option to use assembly language programming or mixed assembly/C programming. To address these issues newer development environment such as the CodeWarrior IDE (Freescale semiconductor, formerly known as Motorola), Code Composer Studio IDE (Texas Instruments) and High-performance Embedded Workshop (Renesa) provide fully Integrated Development Environment (IDE). To get you up to speed with the basic features available in HEW, an example is given in section 5.
5. HEW software development process
There are two modes to operate the H8/38086F CPU board (CPUBD-38086F); namely BOOT mode and USER mode. This can be done be selecting the appropriate jumper setting as shown in figure 4.3.
BOOT mode:
Boot mode is necessary under the following operations:
(i) To upgrade or recover the monitor program
(ii) To store stand-alone user program.
During boot mode flashing, the boot program in the BOOT MAT of the MCU (special ROM hidden from user) receives a write control program from the host PC and stores it in the internal RAM of the MCU. The boot program then erases the entire internal flash memory and transfer control to the write control program. The write control program now coordinates with the host machine to receive the application program, e.g. the monitor code or the user code, and saves it into the flash memory.
1
Host machine
Application program
Write control program
│
│
F-ZTAT mircocomputer │
│
SCI
Boot program
Flash memory RAM
↑
Reset status
2
Host machine
Application program
Write control program
↑
│
F-ZTAT mircocomputer │
↓
SCI
Boot Program
Start
Erase entire RAM
flash memory Write control
area program
↑
Reset canceled
3
Host machine
F-ZTAT microcomputer ↕
SCI
Boot program ↗
∕
↙
Flash memory RAM
Application Write control
program program
↑
│ Start
│
Reset canceled
Figure 4.1 : Overview of boot mode.
USER mode:
This mode is used by the programmer to debug his program with the monitor program. User program mode can only be used when the monitor program is resident in the flash memory. If not, monitor program should be downloaded first under boot mode.
During user mode flashing, the monitor program first copies the write/erase control program, into internal RAM and transfer control to the write / erase control program to erase the flash memory block indicated by HEW that will be used. The MCU starts receiving program data from HEW and write to the flash memory. After completing the flash programming, write / erase control program returns the execution control to the monitor program. The monitor program then waits for debugging command from HEW.
Application Start
Program
Write/erase
RAM transfer control
program program
↑
Monitor program
Figure 4.2: Overview of user mode.
D1: User LED
D2 : User LED
RS232 serial interface
MCU
BOOT/USER mode select
Power connector
D3 : Power LED
D4 : BOOT LED
CON1 & CON2 interface connector
Figure 4.3: H8/38086 CPU board.
To understand the concept of microcontroller interfacing, it is necessary to know the internal architecture block diagram of the H8-38086 MCU. There are 11 ports (port 1 to B) available on the Renesas MCU. Figure 4.4 shows the memory map of the MCU. 52 Kbytes of on-chip flash memory is available along with 3 Kbytes of RAM. The H8-38086 employs a 300H 8-bit CPU core with 10 I/O ports for interfacing with the external devices. Most ports are mult-functional with dedicated to different peripherals within the MCU. For example, Port 4 bit 0 is used for TMIF (timer F) and SCK (SPI) functions. However, usually engineer will only be allowed to interface to one device only unless they are multiplexed in time. Hence it is important when designing the interface of a MCU system to consider the needs of all current and future devices.
HD64F38086R
(Flash memory version)
H'0000
Interrupt vector
H'0057
H'0058
ON-chip ROM
(52 kbytes)
H'BFFF
H'C000 Flash memory
H'CFFF
H'D000
H'EFFF Not used
H'F000
Internal I/O registers
H'F09F
H'F0A0
NOT Used
H'F36F
H'F370
LCD RAM (16 bytes)
H'F37F
H'F380
3 kbytes
User area
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 4.4: H8/38086 memory map.
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Connect the RS232 serial interface to the PC, and the power adapter to the power connector. When the power is switched on, the power LED (D3) should light up. Invoke HEW by double-clicking on the HEW icon on the desktop of the PC. A welcome window will be displayed to prompt for creation of project. Select "Browse to another project workspace" (figure 4.5).
Welcome
Options
• Create a new project workspace OK
• Open a recent project workspace Cancel
• Browse to another project workspace Administration
Figure 4.5: HEW welcome menu.
Select under installed directory (\Tools\Renesas\DebugComp\Platform\Emulator\Evb38086\sample\Blinking_LED\ Blinking_LED.hws). This selects a sample project to blink the LED (D1 and D2) on the CPU board.
Upon clicking the [Open] button, figure 4.7 will appears
Blinking LED High performance Embedded Workshop - [blinking_led.c]
void main (void)
{
//Variable declaration
unsigned int ii;
PORT.PMR9.BYTE = 0xF0; //Set as I/O pins
PORT.PCR9.BYTE = 0xFT; //Port 9 as output Port
PORT.PDR9.BYTE = 0xFF; //Turn-off All LED
While (1)
{
PORT.PDR9.BIT.P92 = 0; //Turn-on LED P92
PORT.PDR9.BIT.P93 = 0; //Turn-on LED P93
for (ii=0; ii<0XFFFF; ii++) ; //Delay
for (ii=0; ii<0XFFFF; ii++) ; //Delay
for (ii=0; ii<0XFFFF; ii++) ; //Delay
for (ii=0; ii<0XFFFF; ii++) ; //Delay
PORT.PDR9.BIT.P92 = 1; //Turn-off LED P92
PORT.PDR9.BIT.P93 = 0; //Turn-off LED P93
for (ii=0; ii<0XFFFF; ii++) ; //Delay
for (ii=0; ii<0XFFFF; ii++) ; //Delay
for (ii=0; ii<0XFFFF; ii++) ; //Delay
for (ii=0; ii<0XFFFF; ii++) ; //Delay
}
Re-compile and linked all program to generate abs file, [Build - Build All] Upon completion, a 'Blinking_LED abs' file wil1 be generated in the workspace window.
Go to [Debug - Debug setting]
Under [Target] box, select [38086F CPU Board] and click [OK] (figure 4.8)
A warning dialog box appears, click [Yes] to continue.
Click [OK] to confirm selection of target device
Debug Settings
Debug session
Blinking_LED
Target
Target
38086F CPU Board
Default Debug Format
<none>
Download Modules: Add
OK Cancel
Figure 4.8: HEW debug setting window.
For Default format, select [Elf/Dwarf2] followed by clicking on [Add] button.
Another dialog box appears, enter the following "Offset": 0x00 'Format": Elf/Dwarf2 "Filename": click [Browse] button, select "Blinking_LED.abs"
Click [OK]
Debug Settings
Debug session
Blinking_LED
Target
Target
38086F CPU Board
Default Debug Format
Elf/Dwarf2
Download Modules
File Name Offset Address Format
C:\Hew38086 H'00000000 Elf/Dwarf2
Download Module
Offset OK
H'00000000 Cancel
Format: Browse
Elf/Dwarf2
Filename:
_LED\Blinking_LED\Debug\Blinking_LED.abs
Access size
1
• Download debug information only
Figure 4.9: HEW debug and download window.
Click [OK]
Go to [Download modules], tight click on "Blinking_LED.abs" and select [Download module] as shown in figure 4.10.
Blinking_LED.abs - Download module
Download Memory
Please wait
Figure 4.10: HEW Download Module window.
A "Downloading memory ... Please wait ... " message is displayed.
When the flashing of user program is completed, the CPU board is ready for user to explore its debugging functions .
To run the program, simply select [Debug] button, select [RESET GO].
Software breakpoint is to trap the program execution to stop at a desired command. Upon downloading the code into the memory of the MCU, physical addresses will be assigned to the commands as shown in figure 4.11. For example, to setup a software breakpoint at line 30 (physical address of 0x0840), the user simply have to move the mouse cursor to the point to the brown dot and double click on it. A brown dot will appears to signify that a breakpoint have successfully been set. Upon executing the code, the PC will be stop at the position corresponding to the breakpoint.
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5.2 Single stepping
Another useful debugging tool is the single stepping command. This feature allows the user to run each and every command in sequence of their execution to narrow down the possible fault of the software algorithm. These functions are 'step-in', 'step-over' and 'step-out'. These commands can easily be accessed via [Debug → step-in], the shortcut keys (F11, F10, etc) or from the toolbar menu.
5.3 Viewing CPU register, memory
For debugging, it is also essential to know the content of various CPU registers, memory locations, and control and status of the MCU peripherals. These functions are easily accessible via.
CPU registers: [View → CPU → register]
CPU memory: [View → CPU → memory]
CPU I/0: [View → CPU → I/O]
Perform single stepping through the code and examine the operation associated with each instruction. Monitor the pin P92 (JP4, pin 16) and P93 (JP4, pin 17) using the oscilloscope, observe the effect of each instruction on the signal. You should be able to capture a square wave at these pins when you run the program. When you are single stepping through the code, you are expected to observe that the signal changes between logic '1' and logic '0' depending on the instruction executed. Please record in you log book these observations. Proceed to modify the code to achieve the following
(i) Blink both LED simultaneously.
(ii) Double the blink rate for LED D1 while keeping the blinking rate for LED D2 to be the same (e.g. blink LED D1 at 2Hz and LED D2 at 1 Hz)
6. EXPERIMENT
6.1 Timer based LED module
In this lab session you will be expected to caiTying out the necessary tests on the timer pulse unit (TPU) to control the brightness of the LED.
To create a new project
1. Select [File → New Workspace]
2. Enter the desired [Workspace Name] & [Directory] and click [OK]
3. In Step 1, select [CPU Series → Tiny] & [CPU Type → 38086F] and click [Next]
4. Click [Next] for the subsequent 6 windows (step 2 to 6) to use the default setting.
5. In step 7, enable [Target → 38086F CPU board], and click [Finish].
On the workspace menu, select the "workspace_name.c" file, this will be your main program. Select "intprg.c" file for the interrupt program.
1. Disconnect JP5, wire-wrap pin 20 of JP4 (P12/TIOCA1) to pin 3 of JP5 (D1 of LED). This step essential disconnects the LED D1 from port 9 bit 2 and instead connect the LED to (port 1 bit 2) i.e. TPU output pin high (TIOCA1).
2. To understand how to program the timer unit of H8-38086, it is necessary to investigate the intemal architecture block diagram of the TPU as shown in figure 4.12.
Clock input
Internal clock: φ/1 Common Control logic TSTR TSYR ↔ Module data bus ↔ Bus interface ↔ Internal data bus
φ/4 ╱
φ/16 ╱
φ/64 ╱
φ/256 ╱
φ/1024 → ╱
╱
External clock: TCLKA ╱
TCLKB ╱
TCLKC ↙
Control logic for channels 1 and 2 → Channel 2 TCR TMDR TIOR TIER TSR ↔ Module data bus ↔ TCNT TGRA TGRB
Input/output pins → Interrupt request signals
↘ Channel 1: TGI1A
Channel 1 : TIOCA1 Channel 1 TCR TMDR TIOR TIER TSR ↔ Module data bus ↔ TCNT TGRA TGRB TGI1B
TIOCB1 TCI1V
↗ Channel 2: TGI2A
Channel 2 : TIOCA2 TGI2B
TIOCB2 TCI2V
[Legend]
TSTR: Timer start register TIOR: Timer I/O control regisers
TSYR: Timer synchro regsiter TIER: Timer interrupt enable register
TCR: Timer control regsiter TSR: Timer status register
TMDR: Timer mode register TGR (A,B): Timer general registers (A, B)
TCNT: Timer counter
Figure 4.12: Block diagram of TPU.
3 Features of TPU
• Choice of 6 internal clocks (φ/1, φ/4, φ/16, φ/64, φ/256, φ/1024) or 3 external clocks)
• Toggle output functions
• Counter resetting by a compare match signal
• Three interrupt input sources: two compare match, one overflow
There are two channels (1 & 2) within the TPU which can be synchronised to provide multi-phase outputs. Beside the standard timer functions of square wave generation, input signal monitoring the TPU also upport PWM (pulse width modulation mode. In this exercise, it is required to program the TPU unit to generate a square wave to control the brightness of LED. By configuring the TPU (either channel) in the appropriate mode, the TPU will be capable of generating a square wave signal on one of its designated output pin at a desirable frequency. You are required to establish the relationship between the mode setting of the TPU unit, the counter pre-load register (TGRA, TRGB) and the frequency of the square wave generated by monitoring the appropriate pins on the MCU using the oscilloscope. It is also required to determine the operating range of LED in order to control its brightness.
4. With the aid of a timing diagram, explain the internal operation of the TPU with explicit reference to the clock signal, counter value, and output signal.
5. With the aid of oscilloscope, measure the frequency of the output signal and derive an equation to model the output frequency of the waveform in terms of the counter value.
6. Modify the TPU software to support interrupt. You must include an appropriate timer interrupt service routine (ISR). Develop an ISR to demonstrate a variable brightness control for the LED. The LED is expected to be OFF (or very dim) initially. The LED will slowly increase its brightness until it is fully turned ON and subsequently start to decrease it brightness slowly. The process then repeats itself. (Note: This experiment will be required to control the slew-up/down operation of the stepper motor.)
7. APPENDIX
Preparatory work to be completed before Session 5
You will be expected to design an interface circuit for the MCU to a stepper motor. It is not possible to drive the stepper motor from the MCU directly, a driver circuit is necessary to provide appropriate driving signals to control the stepper motor. A L298N (Dual H-Bridge) is recommended as the driver circuit to control the motor. You are required to wire-wrap the complete circuit prior to lab 5. You must not continue without the wire-wrapping and appropriate routines to test the stepper motor.
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No. 5: Stepper motor interface and control
Experiment 5: STEPPER MOTOR INTERFACE AND CONTROL
1. OBJECTIVES
1) To demonstrate the interface of the MCU to control a stepper motor.
2) To demonstrate acceleration control in software.
2. LABORATORY
Computer Laboratory
3. EQUIPMENT
Description Quantity
IBM Compatible PC 2
High-performance Embedded Workshop version 4.0 1
H8-38086 CPU board 1
L298N: Dual H-Bridge 1
Stepper motor: 17PM-M012V 1
HP54645A Digital Storage Oscilloscope (DSO) 1
Power Supply Unit 1
Multi-meter 1
4. INTRODUCTION
In many control related applications, there is a need to perform some form of mechanical movement/motion which is usually accomplished with a motor. These applications include printers, disk-drive, and many other robotics related work. Motors can mainly be classified into two types: stepper motor and servo motor. While servo motor has gain a significant foothold in various applications due to their simpler interfaced and higher precision control, stepper motor are still widely use as it can be integrated seamlessly with digital circuits (they are control digitally whereas servo motor are controlled by analog signals) and does not require any feedback since the position can be tracked by counting the number of pulses send to the motor. A stepper motor usually comes with 6 wires connecting to the 4 coils used to control the motor.
Generally the number angular positions are equal to the number of poles in the motor. It is possible to double this resolution by using half-steps. Current flows through the coils to generate a magnetic field in the stator. The permanent magnet rotor aligns itself with this field. Four separate cunent drivers and a step control signal are used to control this motor. Figure 5.2 shows the internal representation of a stepper motor.
Coil C
S
Field → |
coils N Permanent
magnet armature
↓ S ↙
↻ ╲
Coil A N N—S Coil B
|
Coil D
Figure 5.2: Internal representation of steeper motor.
There are usually two different stepping modes to control a stepper motor, they are known as the full-step and half-step mode. The half-step mode offer a double positional resolution improvement over the full-step mode. By energising coil C, it will attracts the armature to align with the coil. Next coil C is de-energised and coil B is engerised. This will cause the armature to rotate to the position shown in figure 5.3(b), resulting the motor to rotate by 90°. As you continue this sequence of energising coil C, B, D, A, C, B, D A, ... , the motor will start to rotate. To increase the torque of the motor, it is possible to engerise both coil C and B followed by B & D and then D & A, and then A & C. This effectiveJy doubles the torque by eneTgizing two coi1s at the same time.
Coil C Coil C
S S
| |
N N
S
↻ |
Coil A N N—S Coil B Coil A ↻ N—S N—S Coil B
| |
Coil D Coil D
(a) (b)
Figure 5.3: Low torque mode full-step stepper motor control.
Previously, the armature rotates 90° irregardless of either one coil or two coils are energise. To double the resolution of rotation, it will possible to energise the coils in the following sequence. Coil C, and then coil C & B, coil B, coil B & D, and coil D. With this energisation sequence, the armature will rotate only 45° each time, doubling the resolution as shown in figure 5.4. Similarly, to reverse the rotation, the sequence can be reverse.
Coil C Coil C
S S
| |
N N
S S
Coil A ↻ | Coil B ↻ ╱
N N—S Coil A N N—S Coil B
| |
Coil D Coil D
(a) (b)
Coil C Coil C
S S
| |
N N
↻ N
Coil A N—S N—S Coil B ↻ ╲
Coil A S N—S Coil B
| |
Coil D Coil D
(c) (d)
Figure 5.4: Half-step stepper motor control
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With this sequence of bit patterns, you can readily construct a sequence of bit to be sent to the motor. The pulse width (∆t) of these bit pattern will determine the speed of the motor.
Table 5.1: Bit pattern to control the stepper motor.
Table 5.1 shows the bit patterns required to drive the stepper motor into the 3 different modes of operations. In the full step, low torque mode, each coil is energised in sequence to move the motor in a forward direction. When the energisation sequence is reversed, the motor will move in the reverse direction. For full-step, high torque mode, two coils are energized simultaneously to double the effective magnetic field to attract the rotor, hence doubling the torque. For half-step movement, the bit pattern alternate between low-torque and high-torque mode to achieve higher (double) precision.
In addition to the high/low torque mode, full/half step mode for controlling the stepper motor, you can also use unipolar/bipolar driving mode depending on the type of stepper motor employed. The Minebea 17PM stepper motor is a hybrid model that can be configured to operate in either unipolar or bjpolar mode. To operate this stepper motor in unipolar mode, the centre taps have to be connected to the driving voltage source. In bipolar mode, the centre taps are left unconnected to form two effective coils (instead of four coils in unipolar mode).
Once the requirements for the digital signals to drive the stepper motor are determined, the next stage is to implement an interface circuit to connect the stepper motor to the MCU. The digital signals from the MCU is not capable of driving the stepper due to the high power requirement of each driving signal (0.67 A). To convert these low current control signals from the MCU into high current driving signals to the stepper motor, a motor driver (e.g. L 298N [3]) can be used. The L298N has a dual full-bridge circuit to drive the four coils of a stepper motor in the bipolar mode. A general overview of the interface between the MCU and stepper is shown in figure 5.6. The L298N simply function as switches to energise the respective coil when a logic '1' is asserted on the corresponding switch input.
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MCU Control signals Motor
(Output ports) ───────────────→ Driving ─────────→ Stepper
Clock/Drive Circuit Drive Motor
sequence sequence
——————————————————————
1a| |
•-|-switch-←Imax = 0.67A-|- Red ----
Signals from | | | ◯
the MCU to | |- Black---| ↙
turn off | | | |
switches | | | | Center tap
1b| | | |
•-|-switch-←Imax = 0.67A-|- Yellow-- |
| | ↓
| | ————————————
2a| | | | |
•-|-switch-←Imax = 0.67A-|-- Brown Black Orange
| | | | |
| | -- |
2b| | |
•-|-switch-←Imax = 0.67A-|——————————————————
| |
| Motor driving |
| circuit |
| (e.g. L298N) |
| |
——————————————————————
Figuare 5,6: Driver circuit for stepper motor.
As high current signals are required to drive the stepper motor, a separate power source is used to drive the motor. In addition to the driver circuit, as the energisation and de-energisation of magnetic coils will generate back emf (electro-motive force) that could potentially damaged the motor and dJiving circuit, 8 diodes are used for such protection.
Issues with stepper motor control
1. Non-overlap time
As part of output pattern switching, a through-current protection period n (non-overlap time) is inserted. The turn-off delay that occurs upon excitation phase switching can destroy a driver. To prevent this, a non-overlap time is inserted to allow for the time delay. This non-overlap time delay ensures that when switching between different phases, hence, not more than two coils are energized at the same time.
Observe using the oscilloscope for any possible overlap time in the output sequence of signals used to control the stepper. A possible solution is to use two separate
instructions to firstly de-engergise the coils prior to engerising the coils. This will ensure the non-overlap time (n) will take at least 1 instruction cycle.
2. Slew-up and slew-down operation
Slew-up/slew-down operation maintains the synchronization of the motor. Out-ofsynchronisation means that if a series of short-cycle pulses are suddenly output to
operate the motor, the motor may not be able to handle the load and will not rotate. Slew-up and slew-down operation is used to avoid this problem. The following
explains the principle of the operation.
• The pulse cycles are gradually shortened to output the specified number of pulses (slew-up operation).
• The specified number of pulses are output at a regular pulse cycle (constant-speed operation).
• The pulse cycle is gradually extended to output the specified number of pulses (slew-down operation).
The requirement for slew-up and down operations can be understood by studying the torque-speed characteristics of the stepper motor. Below a pulse rate of approximately 300 pps (pulse per second), the torque is consistent. As the pulse rate is increased beyond 300 pps, the torque starts to decrease linearly. The requirement for performing slew-up and down operation is the same concept of driving a manual car. You start off at gear 1 with high power but low speed. As the vehicle accelerate and gain momentum, you can change to a higher gear to increase the speed (with a reduction in torque). A pulse rate of 300 pps corresponding to 90 rpm (1 pulse = 1. 8°, therefore, 300 pulses = 540° per second or 1.5 revolution per second = 90 rpm). The speed of the stepper motor is directly related to the pulse rate. To perform slew-up (acceleration) and slew-down (deceleration), you have to inilially provide a low pulse rate and slower increase the pulse rate when the motor starts to rotate. The rate of increase has to correspond to the torque-speed ratio given in the specification of the motor. Once you have reached the desired speed, you will maintain at that speed. Prior to stopping, you have to slow down to a speed slow enough to stop.
5. EXPERIMENT
1. In this session, you can test your interface and driving circuit for the stepper motor. You should have completed the design and connection to the stepper motor before you start this lab session. Develop a simple software routine to generate a four-phase waveform with a recommended frequency of approximately
150 Hz. Connect the four-phase signals to the oscilloscope to verify the phase assertion sequence and frequency. Connect the four-phase signals to four LEDs to ensure you can light up each LED in sequence prior to any direct connection to the stepper motor. You will have to modify the frequency (e.g. 0.25 Hz to light up each LED for 1 s) to enable visuaJ inspection.
2. Power-up the driver circuit and verify if you are able to rotate the stepper motor.
3. Modify your program to
(i) Reverse the direction of rotation,
(ii) Vary the speed of rotation.
4. Modify your program to accelerate the stepper motor from a low speed to a higher speed, maintain the constant higher speed rotation for a predefined duration and finally decelerate the motor to the initial speed before stopping the motor and hold it in poshion (i.e. lock). You are required to record your observation in the log book with a sketch of the output signal as measured on the oscilloscope. The acceleration or the rate of change of velocity permitted will depend on the characteristic of the stepper motor and the load the motor is driving. You have to derive a suitable acceleration and explain how did you arrive at this value.
6. REFERENCES
[1] Minebea Stepper motor (17PM-M012V) application data sheet.
[2] Douglas W. Jones, Control of stepper motors: A tutorial, University of Iowa, Department of Computer Science, July 2003 (http://www.cs.uiowa.edu/~jones/step).