Cypress SRAM pinouts

Why do Cypress label their address bus on their SRAM out of order compared to industry-standard (JEDEC or EIAJ) parts? E.g. they have A10 as A0, and A0 as A14 for their 32Kx8 part.

It this like how Texas Instruments use to reverse the data bus bit ordering, just to be different?

Regardless of the physical connection between the host device and a Cypress SRAM not matching up, I think the change of address bus pins shouldn't matter. Would it?

This is the most intriguing thread on world4ch at the moment

waut cypress like the skydiveing device

Regardless of the physical connection between the host device and a Cypress SRAM not matching up, I think the change of address bus pins shouldn't matter. Would it?
Not at all.
Dunno for the reason of the change, but maybe incompatibility is what they're aiming at.