>>20
RS and below are available to OEMs and the like. I think you'd have to be an Intel employee to get TS info, not sure about that.
>>13
I don't think I can tell you.
>>10,11
U MAD RISCFAGS?
Here's a funny story; I recently had to talk some sense into a friend's kid's CS professor who decided to give an assignment about memory alignment - you were supposed to compile and run this C program, which would test reading/writing memory with different alignments, and then explain the results. It's "common knowledge" and what's taught in the class, that you should see much slower results for unaligned vs. aligned, but databusses are so wide now, and there have been so many improvements to other things since, that you really only get hit once with any noticeable penalty for crossing a cacheline boundary. Not surprisingly, all the students who had any reasonably recent (i.e. Nehalem+) CPU would get basically NO difference in timing from the program, and they were all deducted marks for "incorrect results". It turns out the professor was still using a Netburst, where his test program would show a huge difference, but he hadn't tried anything newer...