Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

>>11
In RISC processors, each instruction has fixed length (e. g. machine word (e. g. 32 bits)).  In CISC processors, there may be instructions of any length, from one byte (e. g. octet) to as many bytes as the power of N in nd=2^N where nd is the maximum amount of dicks that penetrated processor designer's ass simultaneously.