Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

>>10
Fixed-length RISCs certainly have a sparse (SPARCse?) opcode space, which makes them need more memory bandwidth than CISCs with variable-length instructions; they're quite wasteful of opcode space in that way. They usually compensate with more cache and higher clock frequency, which worked OK until a few years ago.

Kindly explain this good sir. I don't understand.