RISC

/prog/, I'm working on a RISC instruction set that is more RISC than any RISC out there. I've devised an instruction format, plus fifteen core instructions that should suffice for any programming out there. The instruction format, instruction forms, and instructions can be found here:

http://jsbin.com/ekuwap

Any comments or suggestions?

>>75
From the instruction set, your CPU has absolutely no memory protection/paging/etc. so I'm assuming it's a simple "open" type like a Z80 or 6502. If you access memory that doesn't exist you would just read the value from a floating databus (FFs if there's termination/pullups, other values are possible but it doesn't matter here) and try to write it to the same nonexistent location, so nothing actually happened.

and's `src' is a register reference, not an immediate value, so you can't just `and r*, 0b11111'. Same goes for or.
Read up on boolean algebra identities. Specifically idempotence.