RISC

/prog/, I'm working on a RISC instruction set that is more RISC than any RISC out there. I've devised an instruction format, plus fifteen core instructions that should suffice for any programming out there. The instruction format, instruction forms, and instructions can be found here:

http://jsbin.com/ekuwap

Any comments or suggestions?

>>74

m would seem to work given that the two register references are the same, and thus their register values are equal, and thus the effective addresses are equal. However, what if the register value represents an effective address that is outside the available memory? It would have undefined behaviour or crash.

and's `src' is a register reference, not an immediate value, so you can't just `and r*, 0b11111'. Same goes for or.

Therefore, it's 1120, with nop, r and jc.