HAHAHAHA
YOU THINK YOURE THOUGH UH ?
I HAVE ONE WORD FOR YOU
THE FORCED BIAS OF THE TRANSISTOR
GET IT ?
I DONT THINK SO
YOU DONT KNOW ABOUT MY OTHER RESISTOR I GUESS ?
ITS A MEMISTOR
AND IS PRONOUNCED ``FAGGOT''
OK YOU FUQIN ANGERED AN EXPERT ENGINEER
THIS IS /ee/
YOU ARE ALLOWED TO POST HERE ONLY IF YOU HAVE ACHIEVED SATORI
ENGINEERING IS ALL ABOUT ``ABSTRACT BULLSHITE'' THAT YOU WILL NEVER COMPREHEND
I HAVE HAND SOLDERED BGAS
IF ITS NOT DONE YOU HAVE TO
TOO BAD VHDL IS SLOW AS FUCK
BBCODE AND VERILOG ARE THE ULTIMATE LANGUAGES
ALSO
WELCOME TO /ee/
EVERY THREAD WILL BE REPLIED TO
NO EXCEPTION
Name:
Anonymous2009-10-08 6:34
AEROSPACE ENGINEER WAS HERE, ELECTRONIC ENGINEERS IS LOSER
>>8
Verilog is for effeminate engineers. VHDL provides much better abstraction and compartmentalisation. I do however concede that Verilog might be better-suited for idiotic gate-level description.
Name:
Anonymous2010-06-12 19:33
entity my_anus is
port (
clk : in std_logic;
hax : out std_logic
);
end my_anus;
architecture hax_my_anus of my_anus is
signal my_anus_internally : std_logic := '0';
begin
hax_it : process
begin
wait until rising_edge(clk);
my_anus_internally <= not my_anus_internally;
end process;
hax <= my_anus_internally;
end hax_my_anus;