ITT: Make your own instruction set.

Make your own instruction set for your own made up processor.  How many bits can it access?  What kind of tasks will it be used for?  Bonus points for making an implementation in sepples, FIOC, lisp, or other GENERAL PURPOSE SCALABLE COST-EFFECTIVE ENTERPRISE QUALITY PROGRAMMING LANGUAGES_{(such as java)}


main = do eax <- 12
          add e
          inx h
          m <- a
          .
          .
          .
etc.

BONK

My processor shall contain a single memory location, BUFFA, and its instruction set shall support the following primitives: a, b, c, d, r, n, $, | and ;.

It can be used for any imaginable computation.

>>4
That seems oddly familiar...
[spoiler]_{Are you that guy from that thread?}[spoiler]

a LANGUAGE is only turing COMPLETE if i_t can implement itself.

subtract and branch if negative bitch.

My instruction set would include the ability to create classes and subclasses, and duck typing will be enabled by default. Everything would be an object. The code would need to be indented one tab for everything, except branches. If you don't indent properly, the program will throw an exception (Yes, my instruction set includes throwing exception capabilities).

If the community (Yes, my instruction set would be super popular and the website for it would have forums and a chatbox so that the community can decide, Instruction Set 2.0, if you will) wants Monad support, I will add support for monads too.

>>8
That would make one damn expensive processor.
my instruction set will only contain add  jump  and  and.

Mine will be a complete implementation of ANSI sepples.  only entirely interpreted.

AnonX86 will fully conform to the IA32 standard, ignoring the stuff about multibyte instructions.  Also, registers will be dynamically sized to hold whatever the user enters, rather than enforcing archaic hard-coded limits.  It will run faster than the bloated Core2 and be implemented in only 7 transistors.

Mine will be completely based on interrupts, where everything is an interrupt.

>>12
Even the interrupts are interrupts.

>>11
I've always wondered what it'd be like to write code for a processor with bit-level variable-length instructions. You could pick the opcodes of the most common instructions to be the shortest, and the least commonly used to be the longest.

>>14
Your C compiler for this CPU would look like ass

[/code]
int8
int7
int6
int5
int4
int3
int2
boolean
long boolean
[/code]

long boolean

[b]typedef   long unsigned boolean*[/b] Bool_t;

My dream processor is a CPU with an insane number of cores, like 2048 or 4096, that are however extremely simple and can be dynamically combined in any way.

Each core has something like 8 local registers, and 8 "addressors."  Each instruction targets an addressor, further instructions can determine whether this addressor is connected to a local register of that core, a local register of another core, cache RAM, external RAM, or I/O space.

One addressor is always connected to a local register.  This is known to the core as the accumulator, or A.  Another is always zero and is known to the core as Z.

The operations on each core are extremely simple, like only: OR, XOR, AND, NAND, INC, DEC which perform the operation on 2 addressors and send it to a third.  Each instruction can be performed either unconditionally, or only be performed if another addressor is 0.  A third modifier determines how the core gets its next instruction; either the address specified in an addressor or the address pointed to by an addressor.  Such address is optionally incremented after control is passed to it.

The bit width of the addressors determines the maximum addressable memory space of the CPU.

Operands can be an addressor or immediate data.

Addressors are written as A0-A7.  Accumulator is just A.

So you have basic op OR, XOR, AND, NAND, NOT, INC, DEC + 3 operands, optional conditional specifier, and next instruction modifier. 

OR.A3z[A4] A0,A1>A2
 OR addressors A0 and A1 and send result to A2 IF A3 is zero, get next instruction from addressor A4
DEC[A4] A2>A3
 Decrements addressor A2 and sends it to A3 unconditionally, get next instruction from addressor A4
XOR[@A4] A5,A6>A
 Exclusive OR's addressors A5 and A6 and sends result to accumulator.  Fetches value pointed to by A4 and gets next instruction from it
JUNCT A3>resource,which_of_resource
 Junctions a addressor to a resource.  Resources are implementation dependent but 0 is always core local registers.  1 may be RAM, 2 may be I/O space, etc.
JUNCT A3,0,3
 Connects addressor A3 to local register 3.
JUNCT A3,1,2205
 If 1 represented system RAM, A3 is now connected to it.
JUNCT A3,4097,2
 If 4097 represented core #2's register set, A3 is now connected to core #2's local register 2.
SP
 Sets protection mode.  A lower-numbered core cannot connect local registers to this core.
CP
 Clears protection mode.  Any core can connect local registers to this core.

Synchronization between cores is achieved by connecting a register or two to local registers of other cores

>>14
EXPERT HUFFMAN OPCODING

My instruction set would include support for matrices. And in addition to the regular registers, there will be matrix registers (3x3 or 4x4) and matrix operations built in.

My instruction set would include instructions for generating rounded corners and stripping the last vowels out of strings.

>>11
Cudder?

>>22
Car?

A purely functional assembly language.

eval, apply

yo guys i heard you like instruction sets

SICP - Conjure the spirits of the computer

mine has only the AND instruction.

>>28
turing plcompletee?D

come on /prog/, you do better then this.

Maybe something like Thumb-2, but with more registers and 64-bit. Simple to generate code for, unambigous.

4 bit processor

One of these bitches:
http://en.wikipedia.org/wiki/SCAB_computer

>>33
Imagine 256 of them in parallel.

>>34
but what the hell does the arm instruction do?

The ultimate processor needs only a single instruction: DWIM

>>35
stupid fuck, it's right there

>>36
case A: for(i=0,w=0;i< W_SIZE;i++){if(dm[i])w+=1<< i; dm[i]=false;}; pc++;break;

I don't GET IT

Instruction set: S, K.

Bits: limited only by available RAM, but you've got to implement Peano arithmetic first.

Tasks: computation.

Implementation: only shit languages need a software implementation. Real languages like SK combinators can be evaluated on pen-and-paper.

The ultimate processor needs only a single instruction: YHBT

As fortune would have it, I already have one at hand:
BBW    Branch Both Ways
BEW    Branch Either Way
BH    Branch and Hang
BMR    Branch Multiple Registers
BOB    Branch On Bug
BPO    Branch on Power Off
BST    Backspace and Stretch Tape
CLBR    Clobber Register
CLBRI    Clobber Register Immediately
CM    Circulate Memory
CMFRM    Come From
CPPR    Crumple Printer Paper and Rip
CRN    Convert to Roman Numerals
DMPK    Destroy Memory Protect Key
DO    Divide and Overflow
EPI    Execute Programmer Immediately
EROS    Erase Read Only Storage
HCF    Halt and Catch Fire
IBP    Insert Bug and Proceed
INSQSW    Insert into queue somewhere (for FINO queues [First in never out])
PDSK    Punch Disk
PI    Punch Invalid
PVLC    Punch Variable Length Card
RASC    Read And Shred Card
RTAB    Rewind tape and break
RWDSK    rewind disk
SPSW    Scramble Program Status Word
WBT    Water Binary Tree