Instruction Set Micro-Optimizations

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

>>24
For some embedded work, interrupt latency (or at least predictable latency) can be critical. On Cortex-M3 LDM/STM can be interrupted halfway through execution, unless it's a conditionally executed instruction in which case it's cancelled and restarted.

If the add instruction has a 1 cycle throughput (like your archetypal MIPS 5-stage pipeline), there's no performance lost, and special-casing doesn't gain you anything either. When going superscalar/OoO it's probably worth recognizing $zero for dependency tracking and register renaming purposes.