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Instruction Set Micro-Optimizations

Name: Anonymous 2012-11-28 18:01

I've always been interested in these, even if few people have a chance to experiment with them, so, yeah, let's do it.

Some 6502 derivatives feature dedicated store 0 and load 0 instructions, which saves a byte and (possibly, I don't remember) a cycle for a very common operation. Neat.

A lot of RISC architectures, on the other hand, feature a dedicated 0 register for this purpose -- iirc, in MIPS, register 0 is always 0. It seems at first glance that this would be more general and useful than load/store 0 instructions, but I'm having trouble thinking of a use for the register besides loading and storing 0 values. On second thought, maybe it's a waste of a register.

Name: Anonymous 2012-11-29 8:20

>>13
At first I thought you meant Thumb on ARM, then I realized there's MIPS16e...
Anyway, here's some interesting data:
http://www.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf
tfw i386 master race

where nd is the maximum amount of dicks that penetrated processor designer's ass simultaneously
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