Name: Anonymous 2012-07-12 6:34
The specifications for the DCPU-16 1.7 can be found here.[0]
Expected clock frequency: 100 kHz
RAM: 128ko (128k octet, 64k 16-bit words)
Tile-based Video RAM of 32x12 tiles defined by 128 4x8 characters stored in RAM
Eight general-purpose registers, almost fully symmetric. (The only difference is in the STI and STD commands, which act as a SET while incrementing and decrementing, respectively, I and J.) Immediate, Absolute, PC-relative, Indirect, Indirect-indexed, Stack addressing modes
16x16->32-bit hardware signed and unsigned multiplication (MUL and MLI), 16-bit hardware signed and unsigned division (DIV and DVI), no BCD, full 16-bit overflow register.
36 opcodes defined, room for more.
No traps or MMU.
Hardware/Software interrupt system. Capable of queuing 256 interrupts.
[0] http://pastebin.com/raw.php?i=Q4JvQvnM
[1] http://0x10cwiki.com/wiki/DCPU-16
Expected clock frequency: 100 kHz
RAM: 128ko (128k octet, 64k 16-bit words)
Tile-based Video RAM of 32x12 tiles defined by 128 4x8 characters stored in RAM
Eight general-purpose registers, almost fully symmetric. (The only difference is in the STI and STD commands, which act as a SET while incrementing and decrementing, respectively, I and J.) Immediate, Absolute, PC-relative, Indirect, Indirect-indexed, Stack addressing modes
16x16->32-bit hardware signed and unsigned multiplication (MUL and MLI), 16-bit hardware signed and unsigned division (DIV and DVI), no BCD, full 16-bit overflow register.
36 opcodes defined, room for more.
No traps or MMU.
Hardware/Software interrupt system. Capable of queuing 256 interrupts.
[0] http://pastebin.com/raw.php?i=Q4JvQvnM
[1] http://0x10cwiki.com/wiki/DCPU-16