VHDL

    Boolean logic :          {'0', '1'};
    Troll logic : { 'U','X','0','1','Z','W','L','H','- ', }

PORTMAP( 0=>d, 1=>i, 0=>c, 1=>k );

       BONUS

Time
Continuous
MIKOsan
Clear

TOTLE

I use 'Z' non-ironically in my code.

Found an example:




LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_unsigned.ALL;


ENTITY tristate IS
    PORT(    sram_io                : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
            sram_te, sram_fe    : IN STD_LOGIC;
            sram_f                : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
            sram_t                : IN STD_LOGIC_VECTOR (7 DOWNTO 0));
END tristate;

architecture tristate of tristate is

BEGIN
    sram_f <= sram_io WHEN (sram_fe = '1' AND sram_te = '0') ELSE (OTHERS => 'Z');
    sram_io <= sram_t WHEN (sram_te = '1' AND sram_fe = '0') ELSE (OTHERS => 'Z');
END tristate;

Actually I'm going to ask about this: As mentioned above, I use Z in my code. I have never, nor have I ever heard of anybody doing this, used any of the other values of STD_LOGIC.

Have any of you used any of the others? Why?

Verilog > VHDL

I don't think you'll ever need to use them as long as you're doing "FPGA programming".

>8

Why _else_ would I use VHDL?

That's a legitimate question btw - if you aren't joking, I honestly don't know what else I'd use VHDL for.

what are you programming?
i once programmed a venting machine

DUBS MOTHERFUCKER DUBS MOTHERFUCKER DUBS


    Troll logic : { 'U','X','0','1','Z','W','L','H','- ', }
syntax error

>>9
Simulating whole systems or external interfaces. They're not useful for synthesis, but that's not even what the language was designed for.