RISC

/prog/, I'm working on a RISC instruction set that is more RISC than any RISC out there. I've devised an instruction format, plus fifteen core instructions that should suffice for any programming out there. The instruction format, instruction forms, and instructions can be found here:

http://jsbin.com/ekuwap

Any comments or suggestions?

Presenting the third version of my RISC ISA:

http://jsbin.com/ekuwap/3

Changes:

- the opcode field is split into two halves; instructions that want 8-bit immediates can use a three-bit opcode
- the `i' instruction now shifts a register 8 bits to the left, and loads an 8-bit immediate into it
- `j' has been renamed to `jc' and a new, unconditional `j' is born because there is no way to do an unconditional jump with the old `j'
- a new `r' instruction is added to move among registers
- the comment column is cleaned up with clearer meanings