>>52,54
All of those can be represented by
100010ds /r. Saying that they are not the same MOV instruction is like arguing that
ADD EAX, 5 and
ADD EAX, 10 are not the same ADD instruction.
Now MOV immediate to register, MOV immediate to memory, MOV Sreg and MOV moffs have their own opcodes. MOV CRx and MOV DRx are even handled as seperate instruction in the Intel manuals.
But even with this, x86 assmebly is very WYSIWYG: ``One of the design goals of NASM is that it should be possible, as far as is practical, for the user to look at a single line of NASM code and tell what opcode is generated by it.''
The only exceptions are for labels (optional, if you are insane) and for optimization (optional). So there is an injective 1-to-1 mapping of a line of x86 assembly to x86 machinecode.
But I'm sure you were all very excited on /g/ about compiling BFS.