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MIPS Assembly code

Name: Anonymous 2011-02-19 20:48

I've been handed an assignment that looks like this and I have no fucking clue how to even get started, it involves taking in a string and determining if it's the longest palindrome. Couldn't find anything else helpful online so thought I might as well come here.

To practice MIPS calling conventions, you must implement 3 functions called “get_to_end” “get_longest,” and  “is_ palindrome:”

•    get_to_end (30 points): It accepts one argument stored in $a0 which is the starting address of a string. It should return two values. In $v0, it should return the address of the last character of the string. In $v1 it should return the number of characters in this string. 
 
•    is_ palindrome (40 points): It accepts one argument stored in $a0, which is the starting address of a string. It should return two values. In $v0, it should return 0 if the string is not a palindrome, and 1 if it is a palindrome. In $v1 it should return the number of characters in this string. Inside it must call “get_to_end” (because obviously it is useful).

•    get_longest (30 points): It accepts two arguments stored in $a0, and $a1, respectively. $a0 is the starting address of an array of 32-bit numbers; $a1 is the number of elements in this array. Each element in this array is the starting address of a string (which may or may not be a palindrome). It should return one value in $v0 which is the starting address of the longest palindrome in the array. Inside it must call “is_ palindrome” for obvious reasons. It should not all “get_to_end.”

Name: Anonymous 2011-02-20 0:42

>>16
http://infocenter.arm.com/help/topic/com.arm.doc.genc007826/Barrier_Litmus_Tests_and_Cookbook_A08.pdf

It almost has a one-to-one mapping with the new fine-grained C1x and C++0x memory models for C and C++, with the exception of no bidirectional fencing.

http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2324.html

But on the other hand, ARM is future proofed for NUMA and heterogeneous computing environments, allowing you to isolate memory fences to the scope of NUMA nodes. In fact, OMAP5 from TI will be a NUMA design, with dual-core ARM Cortex A15s and dual-core ARM Cortex M4s for dedicated DSP and vector processing [single-precision floating point SIMD].

x86/x86-64 is quite fucked in this regard, and it's one of the reasons why Larrabee never delivered the performance it promised.

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