Name: Anonymous 2010-05-09 17:30
Dearest /prog/, I have come upon a problem with
I have a directory tree with a Makefile in the base dir, and similar Makefiles in each subdirectory. The Makefiles each define a few variables (standard stuff like OBJS, CFLAGS, LIBS, etc.); but the base Makefile also has special TARGET and SUBDIRS variables (each subdirectory could also potentially define SUBDIRS themselves).
I have also a generic Makefile include file that decides what to do with all these variables (mostly just target rules). It can also tell whether TARGET is defined, and then choose not to link all the OBJS together if it isn't.
The problem is with SUBDIRS. What I ultimately want to do is go through each subdirectory, cd and make there, and somehow find out what objects were created in order to append them to the OBJS list for the base make process and finish compiling the TARGET.
But I have not found a way to inherit backwards. As far as I know, each child
Or, perhaps, include make directives within target rules, which I'm not sure can be done.
This post has descended into a thought process dump, so I'll wrap it up now. Have any of you come across a similar problem, and how have you solved it? I've never used make for large projects, but I'm comfortable with it - and would be mildly reluctant to switch on the basis of a single anusrider saying simply "Use this alternative".
make (yes, now I have two problems, but that is beside the point).I have a directory tree with a Makefile in the base dir, and similar Makefiles in each subdirectory. The Makefiles each define a few variables (standard stuff like OBJS, CFLAGS, LIBS, etc.); but the base Makefile also has special TARGET and SUBDIRS variables (each subdirectory could also potentially define SUBDIRS themselves).
I have also a generic Makefile include file that decides what to do with all these variables (mostly just target rules). It can also tell whether TARGET is defined, and then choose not to link all the OBJS together if it isn't.
The problem is with SUBDIRS. What I ultimately want to do is go through each subdirectory, cd and make there, and somehow find out what objects were created in order to append them to the OBJS list for the base make process and finish compiling the TARGET.
But I have not found a way to inherit backwards. As far as I know, each child
make process is blissfully unaware of its parent. That means I must do this from the base process (I'm not sure of make's loop constructs):for i in $(SUBDIRS); do \
include $i/Makefile
$(OBJS) += $(CHILD_OBJS) # ???
doneOr, perhaps, include make directives within target rules, which I'm not sure can be done.
This post has descended into a thought process dump, so I'll wrap it up now. Have any of you come across a similar problem, and how have you solved it? I've never used make for large projects, but I'm comfortable with it - and would be mildly reluctant to switch on the basis of a single anusrider saying simply "Use this alternative".