Name: Anonymous 2007-06-28 10:20 ID:wrWqgxab
I'm scared.
- A Thermal Interrupt is Not Generated when the Current Temperature is Invalid
- REP Store Instructions in a Specific Situation may cause the Processor to Hang
- Concurrent Multi-processor Writes to Non-dirty Page May Result in Unpredictable Behavior
- Cache Data Access Request from One Core Hitting a Modified Line in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior
- Invalid Instructions May Lead to Unexpected Behavior
- FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Address (Alignment <= 0x10h) May Cause FPU Instruction or Operand Pointer Corruption
- Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory Image May Be Unexpectedly All 1's after FXSAVE
- Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue
More info courtesy of Theo here: http://marc.info/?l=openbsd-misc&m=118296441702631
- A Thermal Interrupt is Not Generated when the Current Temperature is Invalid
- REP Store Instructions in a Specific Situation may cause the Processor to Hang
- Concurrent Multi-processor Writes to Non-dirty Page May Result in Unpredictable Behavior
- Cache Data Access Request from One Core Hitting a Modified Line in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior
- Invalid Instructions May Lead to Unexpected Behavior
- FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Address (Alignment <= 0x10h) May Cause FPU Instruction or Operand Pointer Corruption
- Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory Image May Be Unexpectedly All 1's after FXSAVE
- Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue
More info courtesy of Theo here: http://marc.info/?l=openbsd-misc&m=118296441702631