VHDL

Lets see some VHDL programming:

--File: enc83
--Author ANONYMOUS
--Date: Feb 15, 2007
--Provides: VHDL for a 8-3 encoder
entity ENC83 is port(
    I7 : in bit;
    I6 : in bit;
    I5 : in bit;
    I4 : in bit;
    I3 : in bit;
    I2 : in bit;
    I1 : in bit;
    I0 : in bit;
    Y2 : out bit;
    Y1 : out bit;
    Y0 : out bit
);
end entity ENC83;

--Achitecture description
-- V0 = (I0)
-- V1 = (I1)
-- V2 = (I2)
-- V3 = (I3)
-- V4 = (I4)
-- V5 = (I5)
-- V6 = (I6)
-- V7 = (I7)
-- Y0 = (1,3,5,7)
-- Y1 = (2,3,6,7)
-- Y2 = (4,5,6,7)
architecture dataflow of ENC83 is

    signal V: bit_vector (7 downto 0);

begin

    V(7) <= I7;
    V(6) <= not I7 and I6;
    V(5) <= not I7 and not I6 and I5;
    V(4) <= not I7 and not I6 and not I5 and I4;
    V(3) <= not I7 and not I6 and not I5 and not I4 and I3;
    V(2) <= not I7 and not I6 and not I5 and not I4 and not I3 and I2;
    V(1) <= not I7 and not I6 and not I5 and not I4 and not I3 and not I2 and I1;
    V(0) <= not I7 and not I6 and not I5 and not I4 and not I3 and not I2 and not I1 and I0;
   
    Y0 <= V(1) or V(3) or V(5) or V(7);
    Y1 <= V(2) or V(3) or V(6) or V(7);
    Y2 <= V(4) or V(5) or V(6) or V(7);

end architecture dataflow;
   

Verilog > VHDL