VHDL issues

i'm making a cache for my VHDL class. problem is i'm a moron and apparently don't understand VHDL at all. so there is

    tag_ram: entity    work.tag_RAM(behav)
        port map(address => Paddress(9 downto 2),
            WRITE_ACTIVE_HIGH => NOTPRW,
            ENABLE => TAGENABLE,
            new_tag => Paddress(15 downto 10),
            tag => TAGDATAOUT);

but the only important part of this is that when TAGENABLE is high then TAGDATAOUT is supposed to end up with some value set to it, it does so through this piece of code:


    main : process(address, WRITE_ACTIVE_HIGH, ENABLE, new_tag) is
    begin
        if (WRITE_ACTIVE_HIGH = '0' and ENABLE = '1') --read
        then
            tag <= MEM(to_integer(address)) after 1 ns;
        end if;
        if (WRITE_ACTIVE_HIGH = '1' and ENABLE = '1') --write
        then
            MEM(to_integer(address)) <= new_tag after 1 ns;
        end if;
    end process main;


which for some reason never seems to figure out that TAGENABLE got set to one.  i have report statements in the real version of the code that basically suggest this code gets "stuck" before it can figure out that TAGENABLE went to one. if anyone knows enough about VHDL to guide me i'd be grateful.

actually it's kind of impossible to get good at hardware without also having a solid understanding of higher level programming.  In fact once i finish this cache and an assignment to synthesize an ALU using Leonardo, i have to write a simulator in C. 

It's going to require me reading in a netlist and then running a simulation.  part of it requires me to scan/lex and sadly the scanner and lexer i made way back in systems programming never worked very well to begin with.  does anyone have a recomendation for something i could easily include in Gcc?

Oh, and adding to the recent response, i do ok with basic C examples, but once you get to really abstract stuff like we did in software engineering this semester, i just get sick of it and want to go back to my wires and xor gates.


oh, and one more thing.  I've finally managed to get myself to the point where I'm writing data out of the ram, but unfortunately for the first couple calls nothing new is going to be written.  Essentially since the cache is starting off uninitialized the first couple mem calls will be empty and therefore right a string of 'U' to something that was already a string of 'U'.  So ye VHDL gurus plz halp me, i know that SIGNALNAME'active is supposed to trigger when the signal has activity even if you're setting it to the same value it already was, but for some reason:

wait until SIGNALNAME'active;

just hangs and never evaluates to true and subsequently progresses.  any suggestions for something else i might use? Basically i want this wait to be broken when the value of this signal is set even if it is set to the SAME value.  Many thanks in advance.