VHDL issues

i'm making a cache for my VHDL class. problem is i'm a moron and apparently don't understand VHDL at all. so there is

    tag_ram: entity    work.tag_RAM(behav)
        port map(address => Paddress(9 downto 2),
            WRITE_ACTIVE_HIGH => NOTPRW,
            ENABLE => TAGENABLE,
            new_tag => Paddress(15 downto 10),
            tag => TAGDATAOUT);

but the only important part of this is that when TAGENABLE is high then TAGDATAOUT is supposed to end up with some value set to it, it does so through this piece of code:


    main : process(address, WRITE_ACTIVE_HIGH, ENABLE, new_tag) is
    begin
        if (WRITE_ACTIVE_HIGH = '0' and ENABLE = '1') --read
        then
            tag <= MEM(to_integer(address)) after 1 ns;
        end if;
        if (WRITE_ACTIVE_HIGH = '1' and ENABLE = '1') --write
        then
            MEM(to_integer(address)) <= new_tag after 1 ns;
        end if;
    end process main;


which for some reason never seems to figure out that TAGENABLE got set to one.  i have report statements in the real version of the code that basically suggest this code gets "stuck" before it can figure out that TAGENABLE went to one. if anyone knows enough about VHDL to guide me i'd be grateful.

>>24
Whenever I work with inouts, the only precaution I take is to use a pair of tristate buffers.  You attach the output of one to the inout (for writing), and the input of the other to the inout (for reading).  Then you do a multiplexer-like control signal, with the control going directly to one, and through a NOT to the other.  This lets you use a signal to control whether the inout is an in or an out.