>>92
Synthesize is the right term when generating FPGA or ASIC netlists.
You
compile C code to machine code which is interpreted by the CPU. The machine code is ran sequentially.
You
synthesize VHDL/Verilog/schematics code to netlists which translate into real hardware structures(in the case of ASIC. In the case of VHDL, they just represent the configuration of various cells, but it's still functionally equivalent to the one ran on an ASIC, just an order of magnitude slower(or less). CPUs like x86 are full custom designs which are a lot more optimized(they optimize the schematics at the transistor/cell level, instead of just at the logic gate level) than autogenerated ASICs, because of ZOMGspeed). The netlists are ``ran'' in parallel, because that's just how electircal current works, but even then, most designs are synchronous and are synced by a clock signal, because true parallel async designs are much harder to manage and keep error-free. (In the case of a CPU, you can say that an instruction takes x (as documented) ticks to execute, that would mean it takes that many clock cycles).